The present invention provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes a spin-rinse-dry (SRD) station disposed between the loading station and the mainframe, a rapid thermal anneal chamber attached to the loading station, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system.

Electro-chemical deposition system

A method for forming a tungsten-containing copper interconnect barrier layer (e.g., a tungsten [W] or tungsten-nitride [WxN] copper interconnect barrier layer) on a substrate with a high (e.g., greater than 30%) sidewall step coverage and ample adhesion to underlying dielectric layers. The method includes first depositing a thin titanium-nitride (TiN) or tantalum nitride (TaN) nucleation layer (12) on the substrate, followed by the formation of a tungsten-containing copper interconnect barrier layer (20) (e.g., a W orWxN copper interconnect barrier layer) overlying the substrate. The tungsten-containing copper interconnect barrier layer can, for example, be formed using a Chemical Vapor Deposition (CVD) technique that employs a fluorine-free tungsten-containing gas (e.g., tungsten hexacarbonyl [W(CO)6]) or a WF6-based Atomic Layer Deposition (ALD) technique. The presence of a thin TiN (or TaN) nucleation layer facilitates the formation of a tungsten-­containing copper interconnect barrier layer with a sidewall step coverage of greater than 30% and ample adhesion to dielectric layers. A copper interconnect barrier layer structure includes a thin titanium-nitride (TiN) (or tantalum nitride [TAN]) nucleation layer disposed directly on the dielectric substrate (e.g., a single or dual-damascene copper interconnect dielectric substrate). The copper interconnect barrier layer structure also includes a tungsten-­containing copper interconnect barrier layer (e.g., a W or WxN copper interconnect barrier layer) formed on the thin TiN (or TaN) nucleation layer using, for example, a CVD technique that employs a fluorine-free tungsten-containing gas (e.g., [W(CO)6]) or a WF6-based ALD technique.

Copper interconnect barrier layer structure and formation method

Embodiments of the invention generally provide an electrochemical plating system. The plating system includes a substrate loading station positioned in communication with a mainframe processing platform, at least one substrate plating cell positioned on the mainframe, at least one substrate bevel cleaning cell positioned on the mainframe, and a stacked substrate annealing station positioned in communication with at least one of the mainframe and the loading station, each chamber in the stacked substrate annealing station having a heating plate, a cooling plate, and a substrate transfer robot therein.

Multi-chemistry plating system

Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process. In one embodiment, a portion of the barrier layer is purposely allowed to react with traces of residual oxide at the silicon junction of the contact level feature to form a low resistance connection.

Contact metallization scheme using a barrier layer over a silicide layer

Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.

Electroless deposition process on a silicon contact

An electroplating process for filling damascene structures on substrates, such as wafers having partially fabricated integrated circuits thereon, includes immersing a substrate, under bias, into a copper plating solution to eliminate thin seed layer dissolution and reduce copper oxide, an initiation step to repair discontinuities in a copper seed layer, superfill plating to fill the smallest features, reverse plating to remove the adsorbed plating additives and their by-products from the substrate, a second superfill plating to fill intermediate size features, a second reverse plating to remove adsorbed plating additives and their by-products from the substrate, and a bulk fill plating with high current density to fill large features. The superfill and reverse plating operations may be repeated more than twice prior to bulk filling in order to provide the desired surface morphology.

Dave W. Jentz

Papers

Method of copper electroplating