A process for generating a number representative of an analogue data source (ADS) in which during enrolment a distinctive characteristic of the ADS is measured to obtain physical data (PD). Part of the PD is used to generate a physical value (PV) representative of the ADS. An error correction algorithm (ECA) is applied to the PV to generate error correction data (ECD), which is transformed, using another part of the PD, to generate transform data. During subsequent regeneration of the PV, the distinctive characteristic is re-measured to generate a new set of PD, and a PV is generated using the same part of the PD physical data as was used during enrolment. ECD is generated by transforming the transform data, using the same part of the PD as was used to transform the ECD during enrolment. The ECA uses the regenerated ECD to correct errors in the PV representative of the ADS.

Data processing apparatus and method

Dispositif programmable (Figs. 1, 22) pour des applications de traitement de signaux dans lequel de courtes boucles de donnees numeriques sont traitees d'une maniere repetitive et en parallele. programmable device (Figs. 1, 22) for signal processing applications in which short loops of digital data are processed in a manner in parallel and repetitive. Le dispositif se compose de cinq sous-systemes independamment programmables (Fig. 3) dont les fonctions peuvent etre utilisees simultanement. The device consists of five independently programmable subsystems (Fig. 3) whose functions can be used simultaneously. Le dispositif est destine a etre utilise avec un dispositif numerique multiplicateur (Figs. 1, 32) et un dispositif numerique de memoire (Figs. 1, 34) pour des applications de traitement de signaux telles que des transformations rapides de Fourier et le filtrage du domaine des temps en temps reels ou presque reels. The device is designed to be used with a multiplier digital device (Figs. 1, 32) and a digital to memory device (Figs. 1, 34) for signal processing applications such as fast Fourier transforms and filtering field occasionally real or almost real. Les cinq fonctions paralleles sont 1. introduction et extraction de donnees dans un dispositif de memoire (Figs. 1, 34) entre des registres selectionnes (Figs. 3. 60, 62, 64, 66, 68 et 70); The five parallel functions 1. Introduction and extraction of data in a memory device (Figs 1, 34.) Between selected records (Figs 3. 60, 62, 64, 66, 68 and 70.) 2. introduction et extraction de donnees dans un multiplicateur exterieur (Figs. 1, 32) entre des registres selectionnes et une unite logique arithmetique (ALU) (Figs. 3, 84); 2. introduction and extraction of data in an external multiplier (Figs 1, 32.) Between selected registers and arithmetic logic unit (ALU) (Figs 3 to 84.) 3. deplacer des donnees depuis la sortie d'un multiplicateur jusqu'a des registres selectionnes et l'unite logique arithmetique ALU; 3. move the data from the output of a multiplier up SELECTED registers and arithmetic logic unit ALU; 4. propagation selective de donnees au travers d'une chaine de registres (Figs. 3, 60, 62, 64, 66, 68 et 70) la longueur de la chaine pouvant etre preselectionnee; 4. selective propagation of data through a chain of registers (Figs 3, 60, 62, 64, 66, 68 and 70.) The length of the chain can be preset; et 5. execution d'operations arithmetiques et logiques selectionnees. 5. and execution of arithmetic operations and selected logic. Le dispositif est pourvu d'un ensemble d'instructions (Fig. 4) pouvant definir completement une quelconque des cinq fonctions executables simultanement. The device is provided with a set of instructions (Fig. 4) which can completely define any of the five simultaneously executable functions. La structure du dispositif est modulaire (Fig. 2) de maniere a permettre l'expansion de la longueur des mots de donnees dans l'unite logique arithmetique. The device structure is modular (Fig. 2) so as to allow the expansion of the length of the data words in the arithmetic logic unit. Des signaux de bits de commande produits a l'interieur sont a meme de provoquer explicitement un report ou d'inhiber un report, permettant ainsi un fonctionnement parallele independant ou un fonctionnement avec une longueur de mots etendue sous la commande du programme. control bit signals generated in the interior are even explicitly cause a delay or inhibit a carry, allowing independent operation or parallel operation with a word length extended under program control. Le dispositif complet peut etre realise sous forme de circuit integre dans une The entire device can be realized in integrated circuit form in a

A bit slice microprogrammable processor for signal processing applications

The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reduceing a required amount of calculations when an amount of distortion between a last frame block and a current frame block; in processing a direct memory access at a higher efficiency; in processing a subdivided data calculation at a higher speed; in processing a branch instruction occurring in the pipeline process at a higher efficiency; and in processing an interruption occurring in a repeat process operation at greater convenience, and furthermore in reducing a required amount of calculations through minimum distortion searching processes hierarchized.

Digital signal processor

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for aligning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.

Data processing unit with pipelined operands

A data processing system for processing a sequence of program instructions has two independent pipelines, an instruction pipeline and an execution pipeline. Each pipeline has a plurality of serially operating stages. The instruction stages read instructions from storage and form therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. Both pipelines operate synchronously under the control of a pipeline control unit which initiates operation of at least one stage of the execution pipeline prior to completion of the instruction pipeline for a particular instruction. Thereby operation of at least one instruction stage and one execution stage of the respective pipelines overlap for each program instruction. The instruction and execution pipelines share high speed memory. The pipeline control unit can independently control the flow of instructions through the two pipelines. This is important for operation in conjunction with a microcode storage element which allows conditional branching and subroutine operation. Circuitry also detects pipeline collisions and exception conditions and delays or inhibits operation of one or more of the pipeline stages in response thereto. Under control of the pipeline control unit, one of the independent pipelines can operate while the other is halted.

Data processing apparatus and method employing instruction pipelining

Control for overlapping instruction execution in an arithmetic unit is provided by stepping a sequence of instructions through a plurality of registers connected in cascade and separately decoding each instruction in a register for control of a corresponding stage in one or more data processing paths, each comprising stages through which data being processed is stepped, each stage corresponding to only one register of the control pipeline. The output of the decoder of each instruction register controls the required operations in the corresponding stage of the data pipeline. Automatically indexed indirect addressing is provided by use of pointers for data sources and destinations as required in the execution of every instruction in order to facilitate highly iterative and structured operations on blocks or arrays of data.

David D. Lynch

Papers

Pipe line high speed signal processor

System for addressing and address incrementing of arithmetic unit sequence control system