The problem of extending modern operating systems to run efficiently on large-scale shared memory multiprocessors without a large implementation effort is solved by a unique type of virtual machine monitor. Virtual machines are used to run multiple commodity operating systems on a scalable multiprocessor. To reduce the memory overheads associated with running multiple operating systems, virtual machines transparently share major data structures such as the operating system code and the file system buffer cache. We use the distributed system support of modem operating systems to export a partial single system image to the users. Two techniques, copy-on-write disks and the use of a special network device, enable transparent resource sharing without requiring the cooperation of the operating systems. This solution addresses many of the challenges facing the system software for these machines. The overheads of the monitor are small and the approach provides scalability as well as the ability to deal with the non-uniform memory access time of these systems. The overall solution achieves most of the benefits of operating systems customized for scalable multiprocessors yet it can be achieved with a significantly smaller implementation effort.

Virtual machine monitors for scalable multiprocessors

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.

Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system

On the Internet, different caches may contain copies of objects that have been copied from originating servers when they were accessed by users. Interconnected caches may have different objects stored thereon that might at some time be requested by a client terminal that is connected to a cache other than the one on which the object is stored. Rather than awaiting a request for a particular object and then querying each neighbor cache to determine whether a copy of the requested object is stored thereon, and then downloading the requested object if it is found, information about the contents of the neighbor caches is exchanged between these caches so that when a request for an object is received, the object can be retrieved from the cache in which it is stored. In the alternative, the object may be retrieved from the originating server if, for example, the object stored in a cache is stale based on the date and time it was last modified in the cache.

Inter-cache protocol for improved web performance

A host system includes a multicache system configured within the host system's memory which has a plurality of local and central cache systems used for storing information being utilized by a plurality of processes running on the system. Persistent shared memory is used to store control structure information entries required for operating central cache systems for substantially long periods of time in conjunction with the local caches established for the processes. Such entries includes a descriptor value for identifying a directory control structure and individual sets of descriptors for identifying a group of control structures defining those components required for operating the configured central cache systems. The cache directory structure is used for defining the name of each configured central cache system and for providing an index value identifying the particular set of descriptors associated therewith. The multicache system also includes a plurality of interfaces for configuring the basic characteristics of both local and central cache systems as a function of the type and performance requirements of application processes being run.

Method and apparatus for improving the performance of a database management system through a central cache mechanism

An airline-based video game system includes a multitasking master computer, which preferably stores video game and other application programs on its hard disk. The master computer is coupled to a set of airplane zone control computers which also perform conventional cabin management tasks. The zone control computers receive data from the master control computer and couple data to identified seat controlling processing units (SEBs). Each SEB receives data from, and couples data to, a set of unique seat display units which are associated with each seat in the airplane. The system downloads application software to the seat display units from the master computer. After receipt of a downloading request, the master computer responds by setting up an application program transmission for generating the display menu which appears on each SDU. The initial applications program downloading results in a menu display at every passenger seat which initiated a request. The applications program is then coupled to each SDU for display on its liquid crystal display screen. The display menu advantageously permits each passenger to select between various operating modes including: movies, games, shopping, survey forms, language selection, communication/data processing services. Communication or data processing services permit selection of in-flight phone services, word processing services, and facsimile services.

Airline-based video game and communications system

A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is being processed, and (2) correcting the data inconsistency states so that the operation may be executed in a correct and consistent manner. In particular, the method is adapted to address two kinds of data inconsistency states: (1) A request for a operation from a system unit to main memory when the location to be written to is present in the cache of some processor unit-in such a case, data in the cache is "stale" and the data inconsistency is avoided by preventing the associated processor from using the "stale" data; and (2) when a read operation is requested of main memory by a system unit and the location to be read may be written or has already been written in the cache of some processor--in this case, the data in main memory is "stale" and the data inconsistency is avoided by insuring that the data returned to the requesting unit is the updated data in the cache. The presence of one of the above-described data inconsistency states is detected in a SCU-based multi-processing system by providing the SCU with means for maintaining a copy of the cache directories for each of the processor caches. The SCU continually compares address data accompanying memory access requests with what is stored in the SCU cache directories in order to determine the presence of predefined conditions indicative of data inconsistencies, and subsequently executes corresponding predefined fix-up sequences.

David J. Webb

Papers

Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system