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David J. Zimmerman
Researcher at Intel
Publications - 33
Citations - 865
David J. Zimmerman is an academic researcher from Intel. The author has contributed to research in topics: Registered memory & Semiconductor memory. The author has an hindex of 15, co-authored 33 publications receiving 850 citations.
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Patent
Memory channel test fixture and method
TL;DR: In this article, the memory module can initiate commands and transmit those commands over its downstream memory channel port as if the commands originated from a host connected to the host-side memory channel.
Patent
Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
Raj K. Ramanujan,Dimitrios Ziakas,David J. Zimmerman,Mohan J. Kumar,Muthukumar P. Swaminathan,Bassam N. Coury +5 more
TL;DR: In this article, a system and method for integrating a memory and storage hierarchy including a nonvolatile memory tier within a computer system is described, where PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as far memory.
Patent
Apparatus and method for implementing a multi-level memory hierarchy
Raj K. Ramanujan,Rajat Agarwal,Kai Cheng,Taarinya Polepeddi,Camille C. Raad,David J. Zimmerman,Muthukumar P. Swaminathan,Dimitrios Ziakas,Mohan J. Kumar,Bassam N. Coury,Glenn J. Hinton +10 more
TL;DR: In this paper, a system and method for integrating a memory and storage hierarchy including a nonvolatile memory tier within a computer system is described, where PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as far memory.
Patent
Apparatus, method, and system for implementing micro page tables
Glenn J. Hinton,Raj K. Ramanujan,Cape Scott J,Madhavan Parthasarathy,David J. Zimmerman,Wayne A. Downer,Rajesh S. Parthasarathy,Larry Smith,Robert S. Chappell,Muthukumar P. Swaminathan,Adrian C. Moga +10 more
TL;DR: In this paper, a micro-page table engine is described that is capable of receiving a memory page request for a page in global memory address space, and a translation lookaside buffer (TLB) is used to store one or more memory page address translations.
Patent
Interface for storage device access over memory bus
TL;DR: In this article, a nonvolatile storage or memory device is accessed over a memory bus, and a controller coupled to the bus sends synchronous data access commands to the non-volatile memory device, and reads the response from the device bus based on an expected timing of a reply from the non volatile memory device.