A high-speed transmitter and receiver are provided. In one embodiment, a transmitter comprises a baseband processor structured to receive data and to convert the data into a multiplicity of high and low signal values, with each high and low signal value having a first timing interval. A local oscillator generates a clock signal at a second timing interval and a digital circuit combines the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency. A receiver is configured to receive the signal. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

High data rate transmitter and receiver

In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.

Transmit architecture for wireless multi-mode applications

An integrated low noise amplifier includes an on-chip balun, a line impedance matching circuit and an on-chip differential amplifier. The on-chip balun is operably coupled to convert a single ended signal into a differential signal. The line impedance matching circuit is operably coupled to the primary of the on-chip balun to provide impedance matching for a line carrying the single ended signal. The on-chip differential amplifier is operably coupled to amplify the differential signal and is impedance matched to the secondary of the on-chip balun.

Integrated circuit low noise amplifier and applications thereof

A chip comprises and operational section and an input/output section. The operational section includes a controller. The input/output (I/O) section is coupled to the operational section. The I/O section comprises a transformer and a switching device. The transformer includes a primary side connected to first and second I/O ports and a secondary side connected to the operational section. The switching device is coupled to the controller and between the first and second I/O ports and a bias port, such that, under control of the controller, the switching device connects one of the first and second I/O ports to the bias port.

Transceiver system and method of using same

Apparatus and methods for envelope tracking systems with automatic mode selection are provided herein. In certain configurations, a power amplifier system includes a power amplifier that amplifies a radio frequency signal and that receives power from a power amplifier supply voltage. The power amplifier system further includes an envelope tracker that generates the power amplifier supply voltage based on an envelope signal corresponding to an envelope of the radio frequency signal. The envelope tracker includes a signal bandwidth detection circuit that processes the envelope signal to generate a detected bandwidth signal, and a mode control circuit that controls a mode of the error amplifier based on the detected signal bandwidth.

Apparatus and methods for envelope tracking systems with automatic mode selection

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.

Bias Control for Stacked Transistor Configuration

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Scalable periphery tunable matching power amplifier

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.

Methods and Apparatuses for use in Tuning Reactance in a Circuit Device

A low noise direct conversion transmitter architecture without a post-PA filter is described. A high power/low noise differential LO (110), controlled by a near unity divide ratio PLL (112) for re-modulation protection, is coupled a polyphase quadrature generator (120) generating amplitude-balanced and phase-shifted limited differential LO signals. The quadrature mixers (130 and 132) receive the limited differential LO signals and the filtered differential baseband signals to produce up-converted differential signals. The combiner (168) receives the up-converted differential signals and combines them to produce a differential RF transmission signal. A VCA (174) amplifies the differential RF transmission signal, and the resulting differential signal is converted to a single-ended RF transmission signal through a balun (180). A linear amplifier (184) is coupled to the single-ended RF transmission signal for amplification before radio transmission by an antenna (188).

Low noise architecture for a direct conversion transmitter

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

David Kovac

Papers

Bias Control for Stacked Transistor Configuration

Scalable periphery tunable matching power amplifier

Methods and Apparatuses for use in Tuning Reactance in a Circuit Device

Low noise architecture for a direct conversion transmitter

Cascode amplifier bias circuits