In one aspect there is provided a method. The method may include receiving a first analog radio frequency signal including a signal of interest and an interference signal caused by a second analog radio frequency signal transmitted in full duplex over a channel from which the first analog transmission is received; combining the first analog radio frequency signal and a portion of the second analog radio frequency signal to generate an output analog radio frequency signal characterized by at least a reduction or an elimination of the interference signal included in the output analog radio frequency signal; and providing the output analog radio frequency signal. Related apparatus, systems, methods, and articles are also described.

Single channel full duplex wireless communications

A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

A fully integrated, programmable mixed-signal transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC does not use spiral inductors and instead includes transmission line inductors allowing for improved scalability. Components of the transceiver are programmable to allow the transceiver to switch between different frequency bands of operating. Frequency switching can be accomplished though the content of digital registers coupled to the components.

Programmable radio transceiver

Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a wakeup packet. For example, an apparatus may include circuitry configured to cause a first wireless device to modulate a preamble of a wakeup packet according to an Orthogonal Frequency Division Multiplexing (OFDM) scheme; modulate a payload of the wakeup packet according to an On-Off keying (OOK) modulation scheme over a plurality of OFDM tones; and transmit the wakeup packet to a second wireless device.

Apparatus, system and method of communicating a wakeup packet

A wireless communication device includes, in part, an analog interference cancellation circuit and a controller. The analog cancellation circuit includes a multitude of delay paths each including a delay element and a variable attenuator. The controller dynamically varies the attenuation level of each of the variable attenuators in accordance with the frequency response characteristic of that attenuator to remove a portion of a self-interference signal present in a signal received by the device. The device measures the frequency response characteristic of the communication channel, used in determining the attenuation levels, via one or more preamble symbols. A second portion of the self-interference signal is removed by the device using a multitude of samples of a transmitted signal and a multitude of samples of a signal to be transmitted.

Self-interference cancellation

The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.

CMOS transceiver having an integrated power amplifier

Various methods and corresponding active interference cancellation units are described. These methods and units can perform active interference cancellation in a system including multiple radios. Notably, signals from a first radio can be received as interference at a second radio. The described methods and units can provide interference conditioning, which manipulates an interference reference of the interference at the first radio to approximate an interference observed at the second radio. After tuning of the interference conditioning, the interference can be removed.

Active cancellation of interference in a wireless communication system

A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Fractional and integer pll architectures

A beacon message is wirelessly transmitted from a first device. The first device receives a first response to the beacon message, wherein the first response includes identification values associated with a personal identification device. The first device communicates with a second device associated with the personal identification device. The personal identification device is authenticated based, at least in part, on the identification values and the communication with the second device.

Wireless networking-enabled personal identification system

The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

David Kuochieh Su

Papers

CMOS transceiver having an integrated power amplifier

Active cancellation of interference in a wireless communication system

Fractional and integer pll architectures

Wireless networking-enabled personal identification system

Synthesizer with lock detector, lock algorithm, extended range VCO, and a simplified dual modulus divider