Recent research results have demonstrated the feasibility of full-duplex wireless communication for short-range links. Although the focus of the previous works has been active cancellation of the self-interference signal, a majority of the overall self-interference suppression is often due to passive suppression, i.e., isolation of the transmit and receive antennas. We present a measurement-based study of the capabilities and limitations of three key mechanisms for passive self-interference suppression: directional isolation, absorptive shielding, and cross-polarization. The study demonstrates that more than 70 dB of passive suppression can be achieved in certain environments, but also establishes two results on the limitations of passive suppression: (1) environmental reflections limit the amount of passive suppression that can be achieved, and (2) passive suppression, in general, increases the frequency selectivity of the residual self-interference signal. These results suggest two design implications: (1) deployments of full-duplex infrastructure nodes should minimize near-antenna reflectors, and (2) active cancellation in concatenation with passive suppression should employ higher-order filters or per-subcarrier cancellation.

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Passive Self-Interference Suppression for Full-Duplex Infrastructure Nodes

An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

A compact circularly polarized (CP) co-designed filtering antenna is reported. The device is based on a patch radiator seamlessly integrated with a bandpass filter composed of coupled stripline open-loop resonators, which are designed together as a system. In the proposed design, the patch functions simultaneously as the radiator and the last stage resonator of the filter, resulting in a low-profile integrated radiating and filtering module with a small overall form factor of $\mathbf{0.53{\lambda _0} \times 0.53{\lambda _0} \times 0.07{\lambda _0}}$ . It is shown that the filtering circuit not only ensures frequency selectivity but also provides impedance matching functionality, which serves to broaden both the impedance and axial ratio bandwidths. The designed filtering antenna was fabricated and measured, experimentally achieving an $\mathbf{{S_{11}} , an axial ratio of less than 3 dB and a gain higher than 5.2 dBi over a bandwidth from 3.77 to 4.26 GHz, i.e., around 12.2%, which makes it an excellent candidate for integration into a variety of wireless systems. A linearly polarized version of the integrated filtering antenna was also demonstrated. In addition, further full-wave simulations and experiments were carried out to verify that the designed CP filtering antenna maintains its properties even when mounted on different positions of the human body with various body gestures. The stable impedance and radiation properties also make it a suitable candidate as a wearable antenna for off-body wireless communications.

A Compact, Wideband Circularly Polarized Co-designed Filtering Antenna and Its Application for Wearable Devices With Low SAR

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

From the Publisher:
This book offers a quantitative and design-oriented presentation of the analog RF aspects of modern wireless telecommunications and data transmission systems from the antenna to the baseband level. It takes an integrated approach to topics such as antennas and proagation, microwave systems and circuits and communication systems.

David M. Pozar

Papers

Microwave and Rf Design of Wireless Systems