Starts with a brief review of the history and the application areas considered in the literature. The author then proceeds with introductory modeling examples, behavioral and structural properties, three methods of analysis, subclasses of Petri nets and their analysis. In particular, one section is devoted to marked graphs, the concurrent system model most amenable to analysis. Introductory discussions on stochastic nets with their application to performance modeling, and on high-level nets with their application to logic programming, are provided. Also included are recent results on reachability criteria. Suggestions are provided for further reading on many subject areas of Petri nets. >

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Petri nets: Properties, analysis and applications

Data flow is a natural paradigm for describing DSP applications for concurrent implementation on parallel hardware. Data flow programs for signal processing are directed graphs where each node represents a function and each arc represents a signal path. Synchronous data flow (SDF) is a special case of data flow (either atomic or large grain) in which the number of data samples produced or consumed by each node on each invocation is specified a priori. Nodes can be scheduled statically (at compile time) onto single or parallel programmable processors so the run-time overhead usually associated with data flow evaporates. Multiple sample rates within the same system are easily and naturally handled. Conditions for correctness of SDF graph are explained and scheduling algorithms are described for homogeneous parallel processors sharing memory. A preliminary SDF software system for automatically generating assembly language code for DSP microcomputers is described. Two new efficiency techniques are introduced, static buffering and an extension to SDF to efficiently implement conditionals.

Synchronous data flow

Over the last decade, the Petr i net has gamed increased usage and acceptance as a basic model of systems of asynchronous concurrent computation. This paper surveys the basic concepts and uses of Petm nets. The structure of Petr i nets, thei r markings and execution, several examples of Petm net models of computer hardware and software, and research into the analysis of Petm nets are presented, as are the use of the reachabil i ty tree and the decidability and complexity of some Petr i net problems. Petr i net languages, models of computation related to Petm nets, and some extensions and subclasses of the Petri net model are also bmefly discussed

Petri Nets

The next generation of AI applications will continuously interact with the environment and learn from these interactions. These applications impose new and demanding systems requirements, both in terms of performance and flexibility. In this paper, we consider these requirements and present Ray--a distributed system to address them. Ray implements a unified interface that can express both task-parallel and actor-based computations, supported by a single dynamic execution engine. To meet the performance requirements, Ray employs a distributed scheduler and a distributed and fault-tolerant store to manage the system's control state. In our experiments, we demonstrate scaling beyond 1.8 million tasks per second and better performance than existing specialized systems for several challenging reinforcement learning applications.

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Ray: a distributed framework for emerging AI applications

Programmability with increased performance? New strategies to attain this goal include two approaches to data flow architecture: data flow multiprocessors and the cell block architecture.

Data Flow Supercomputers

A processor is described which can achieve highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor is a step toward a practical data-flow processor for a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnecion that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.

A preliminary architecture for a basic data-flow processor

A processor is described which achieves highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor incorporates practical data-flow processing of a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnection that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.

Data processing apparatus for highly parallel execution of stored programs

A microprocessor-based system serves as a message routing switch for communication between a number of different devices. Any device attached to the switch can communicate with any other attached device through a number of serial and parallel Input/Output ports. Communication between devices attached to the switch is in one of two formats. In a first method of communication, an attached device can be directly associated with another attached device in which case any communication from one is immediately transmitted to the other. In a second method of communication, an attached device communicates with the switch by means of fixed format packets, each of which contains a specification of its destination and error checking capabilities. This second method of communication permits examination of the validity of messages transmitted to or from the switch and enables message retransmission in the case of error.

Digital communications controller with firmware control

Petri nets are investigated as one method of modeling speed independent asynchronous circuits. A study of circuit realizations of Petri nets leads to a demonstration of their usefulness in modeling speed independent operation. This usefulness is emphasized by the design of a speed independent processor from modules developed in the investigation of Petri net implementation.

Petri nets and speed independent design

A computer of unusual architecture is described that achieves highly parallel operation through use of a data-flow program representation. The machine is especially suited for signal processing computations such as waveform generation, modulation, and filtering, in which a group of operations must be performed once for each sample of the signals being processed. The difficulties of processor switching and memory/processor interconnection arising in attempts to adapt Von Neuman type computers for parallel operation are avoided by an organization in which sections of the machine communicate through transmission of information packets, and delays in packet transmission do not compromise effective utilization of the hardware. The design concept is especially suited to implementation using asynchronous logic and large-scale integrated circuits. Application of the concepts to generalized data-flow program languages is under study.

David P. Misunas

Papers

A preliminary architecture for a basic data-flow processor

Data processing apparatus for highly parallel execution of stored programs

Digital communications controller with firmware control

Petri nets and speed independent design

A computer architecture for highly parallel signal processing