Showing papers by "David Padua published in 1989"

Event synchronization analysis for debugging parallel programs

Abstract: One of the major difficulties of explicit parallel programming for a shared memory machine model is detecting the potential for nondeterminacy and identifying its causes. There will often be shared variables in a parallel program, and the tasks comprising the program may need to be synchronized when accessing these variables. This paper discusses this problem and presents a method for automatically detecting non-determinacy in parallel programs that utilize event style synchronization instructions, using the Post, Wait, and Clear primitives. With event style synchronization, especially when there are many references to the same event, the difficulty lies in computing the execution order that is guaranteed given the synchronization instructions and the sequential components of the program. The main result in this paper is an algorithm that computes such an execution order and yields a Task Graph upon which a nondeterminacy detection algorithm can be applied. We have focused on events because they are a frequently used synchronization mechanism in parallel versions of Fortran, including Cray [Cray87], IBM [IBM88], Cedar [GPHL88], and PCF Fortran [PCF88].

Utilizing multidimensional loop parallelism on large scale parallel processor systems

Abstract: Program parallelism and processor allocation issues for parallel processor systems are discussed. Optimal processor assignment algorithms are presented for simple and complex nested parallel loops. These processor assignment schemes can be used by the compiler to perform static processor allocation to multiply nested parallel loops. Speedup measurements for EISPACK and IEEE DSP subroutines that result from the optimal assignment of processors to parallel loops are also presented. These measurements indicate that optimal processor assignments result in almost linear speedups on parallel processor machines with a few tens of processes and significantly high speedups for machines with hundreds or thousands of processors. >

Cedar architecture and its software

Abstract: The Cedar system is clustered shared-memory multiprocessor system The architecture and the main system features of the Cedar system were designed to meet the following goals: (1) to be a general-purpose high-performance machine for parallel processing; (2) to be scalable both architecturally and physically to a very large system; and (3) to be easy to program with a good environment for user support To achieve these design goals, software on the Cedar system plays a very important role The authors describe the relations between the software and the underlying hardware, including the architecture, on the Cedar system >

Problem solving environments

Abstract: The author discusses a few issues regarding programming tools and their interaction. In parallel programming environments the target machine is parallel, and at least some of the tools deal with parallelism by making possible its expression (e.g. a computer for a parallel programming language or a parallelizing compiler). The author discusses the more general concept of problem-solving environments because he believes that in the future, and at least for some applications, the users of these environments will not be programmers or at least will not have to write any programs. Therefore, much of the interaction with the system will be a description of the problem to be solved and not a description of the solution method. >