A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Vertical system integration

2066193 9105366 PCTABS00004 A process for fabricating thin film silicon wafers using a novel etch stop composed of a silicon-germanium alloy (24) includes properly doping a prime silicon wafer (20) for the desired application, growing a strained Si1-x Gex alloy layer (24) onto seed wafer (20) to serve as an etch stop, growing a silicon layer (26) on the strained alloy layer with a desired thickness to form the active device region, oxidizing the prime wafer (20) and a test wafer (30), bonding the oxide surfaces of the test (30) and prime wafers (20), machining the backside of the prime wafer (20) and selectively etching the same to remove the silicon (20 and 22) removing the strained alloy layer (24) by a non-selective etch, thereby leaving the device region silicon layer (26). In an alternate embodiment, the process includes implanting germanium, tin, or lead ions to form the strained etch stop layer (24).

Method of producing a thin silicon-on-insulator layer

A process for preparing a semiconductor member by forming a member having a non-porous monocrystalline semiconductor region on a porous monocrystalline semiconductor region, bonding the insulating surface of a member to the surface of the non-porous monocrystalline semiconductor region, and then removing the porous monocrystalline semiconductor region by etching.

Semiconductor member and process for preparing semiconductor member

A heat spreading apparatus (20) includes a first planar body (22) for attachment to a heat generating surface and a second planar body (21) connected to the first planar body (22) defining a void therebetween. The void contains a vaporizing fluid and includes a planar capillary path (50) and a non-capillary path (32).

Thin, planar heat spreader

A thin epitaxial layer of silicon is disposed on a supporting silicon substrate and a silicon oxide layer or other suitable layer is formed on the epitaxial layer. The substrate, epitaxial layer and oxide layer sandwich is bonded by the simultaneous application of heat and voltaic pressure to another oxidized substrate such that the epitaxial layer is sandwiched between the two substrates with the oxide layer at the sandwich interface. Alternatively, the substrates may be joined by bonding without the use of voltaic pressure by placing the substrates (parent and supporting) at approximately 900° C. The substrates with the epitaxial layer is processed to remove a substantial portion of the silicon substrate with the final portion being removed by etching. When the final portion of the silicon substrate is removed by etching, exposing the epitaxial silicon layer, the etching rate changes dramatically and this is reflected in the byproduct concentration in the etchant solution. The etching process is immediately terminated when the epitaxial layer is fully exposed. After further finishing steps, the resulting product of this method is an epitaxial monocrystalline silicon layer of high crystalline perfection, separated by a silicon oxide layer from a supporting silicon substrate.

David R. Wanlass

Papers

Method of manufacture of an epitaxial semiconductor layer on an insulating substrate