Computer method and apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

Computer method and apparatus for division and square root operations using signed digit

An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimated partial remainder W[j+1] for the next iteration, j+1, as 2*W[j]−Sj+1*D, where W[j] is the estimated partial remainder for the current iteration calculated during the prior iteration, Sj+1 is the quotient bit estimated for the next iteration, and D is the respective divisor bit. The estimated quotient bit for the next iteration is selected based on the calculated partial remainder. In the square-root mode, the first summing device calculates 2W[j]−2S[j]Sj+1, where W[j] is the estimated partial remainder and Sj+1 is the estimated result generated during the current iteration, j. A shift register shifts the value of the estimated result, Sj+1, to generate −Sj+1 2·2−(j+1), which is summed with the result from the first summing device to generate the estimated partial remainder for the square root mode.

Floating point divide and square root processor

A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.

Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operations

A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

Architecture for joint detection hardware accelerator

A method and device divides a dividend by a divisor, the dividend and the divisor both being integers. The method and device determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend, normalizes the dividend and divisor, and calculates NDQ number of quotient digits from the normalized divisor and dividend.

Low latency integer divider and integration with floating point divider and method

An iterative division and/or iterative square root circuit 20 uses quotient digits q j+1 within the calculation that are dependent upon the input divisor D or radicand A and current partial remainder or partial radicand P j for the cycle reached. As the input divisor D or radicand A is fixed throughout the calculation, the critical path through the iterative circuit may be speeded up by preselecting and storing a subset QC of quotient digit values using a primary quotient digit selecting circuit 18, 22 operating in dependence upon the divisor D or radicand A and independently of the partial remainder or partial radicand P j . Within the iterative circuit 20, the quotient digits q j+1 to be used for each cycle can then be selected from this subset QC by a secondary quotient digit selecting circuit 24 in dependence upon the partial remainder or partial radicand P j and independent of the divisor D or radicand A.

Division and/or square root calculating circuit

PROBLEM TO BE SOLVED: To make an iterative division and/or iterative extraction of square root arithmetic circuit fast by selecting a subset of quotient digit values in advance and shortening a calculation time which passes through the critical of operation. SOLUTION: A dividend A is divided by a divisor D to generate a quotient Q. An iterative dividing circuit 20 calculates a partial residue represented as Pj+1 =rPj -qj+1 D first in each iterative calculation. Here, Pj+j is a partial residue after j+1 iteration, (r) a base, Pj a partial residue after (j) iteration, qj+1 a quotient digit depending upon Pj and D, and a Pj a dividend A when j=0. Then a primary quotient digit selecting circuit selects and stores a subset of quotient digits qj+1 which depend upon D and do not depend upon Pj . Then a secondary quotient digit selecting circuit operates to select a quotient digit qj+1 to be used by the iterative dividing circuit 20 from the stored subset of quotient digits qj+1 which depends upon Pj and do not depend upon D.

David Terrence Matheny

Papers

Division and/or square root calculating circuit

Division and/or extraction of square root arithmetic circuit