Mechatronics Technology is a growing career field that deals with the integration of mechanical and electronic components managed by control systems. Mechatronics technicians troubleshoot, maintain and repair mechanical equipment controlled by electrical, electronic and computer systems. These types of systems are increasingly used in a wide variety of manufacturing and industrial settings. Clark College's Mechatronics Technology (MTX) classes emphasize current concepts and technology by providing practical, hands-on experiences with the latest, industry standard equipment. In addition to the technical knowhow needed to maintain and repair equipment, the certificate and degree programs will help prepare students to think critically, function as a successful team member and communicate clearly too internal and external customers.

Mechatronics기술개발 현황과 과제

Differential Fault Analysis (DFA) is one of the most powerful techniques to attack cryptosystems. Several countermeasures have been proposed, which are based either on information or temporal redundancy. In this work, we propose a novel approach based on a Double-Data-Rate (DDR) computation template. A few sample architectures have been implemented: they are compared to other existing architectures and countermeasures, and a thorough dependability analysis is given.

Double-Data-Rate Computation as a Countermeasure against Fault Analysis

The concept of parallel leadership that is introduced in this article derives from a five‐year research project that was first reported in IJEM in 1997. Parallel leadership represents a relationship between teacher leaders and principals that is grounded in the values of mutual trust, shared directionality and allowance for individual expression. It appears to provide a leadership foundation upon which successful school reform can be built. Thus, the lid of what Hallinger and Heck have called the “black box” of school reform may have been prised open.

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Parallel leadership: a clue to the contents of the 'black box' of school reform

Synchronous systems offer a clean semantics and an easy verification path at the expense of often inefficient implementations. Capturing design specifications as synchronous models and then implementing the specifications in a less restrictive platform allow to address a much larger design space. The key issue in this approach is maintaining semantic equivalence between the synchronous model and its implementation. We address this problem by showing how to map a synchronous model onto a loosely time-triggered architecture that is fairly straightforward to implement as it does not require global synchronization or blocking communication. We show how to maintain semantic equivalence between specification and implementation using an intermediate model (similar to a Kahn process network but with finite queues) that helps in defining the transformation. Performance of the semantic preserving implementation is studied for the general case as well as for a few special cases.

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Implementing Synchronous Models on Loosely Time Triggered Architectures

VLSI systems are often constructed from a multitude of independently clocked synchronous IP blocks. Unfortunately, while a synchronous design style may produce efficient block level implementations it does little to support their composition. The addition of asynchronous interfaces to each synchronous block is one way to simplify and strengthen their integration. Asynchronous interfaces allow blocks to be composed without the need to consider synchronisation failure rates, permit data-driven operation and provide greater freedom when designing on-chip buses and networks. This paper surveys the significant body of published work in this area. We highlight similarities between schemes that are often concealed by differences in specification or circuit style. We also present new local clock implementations and provide solutions to mitigate the effect of clock-tree insertion delays. The ultimate goal of this work is to permit multi-clock synchronous systems to be composed simply, robustly and efficiently.

Demystifying Data-Driven and Pausible Clocking Schemes

A technique is proposed to synthesise system behavioural specifications written in VHDL into speed-independent asynchronous circuits constructed using David cells. This technique combines the advantages of logic synthesis and syntax-directed translation techniques. Coloured Petri nets and labelled Petri nets are used as intermediate formats for datapath and control representation. Speed-independent asynchronous circuits are obtained from these nets via direct translation. Several examples demonstrate the viability of the technique, which produces superior results compared with other ones.

Asynchronous system synthesis based on direct mapping using VHDL and Petri nets

A new low-cost low-complexity checker for online testing of asynchronous interfaces in globally-asynchronous locally-synchronous circuits is proposed. The solution is fully based upon the standard gate libraries. The checker itself is fully offline testable. It also provides a fault-locating functionality, which is achieved by combining the online mode with scan techniques.

Low-Cost Online Testing of Asynchronous Handshakes

The authors present a novel circuit implementation of the advanced encryption standard using self-timed dual-rail technology. The design reduces leakage of internal information through balanced power consumption, which is achieved by avoidance of glitches and by data-independent switching behaviour. The design utilises a pipeline structure with built-in controllers and novel, highly balanced security latches.

High-security asynchronous circuit implementation of AES

Portable digital systems need to be not just low power but power efficient as they are powered by low batteries or energy harvesters. Energy harvesting systems tend to provide nondeterministic, rather than stable, power over time. Existing memory systems use delay elements to cope with the problems under different Vdds. However, this introduces huge penalties on performance, as the delay elements need to follow the worst case timing assumption under the worst environment. In this paper, the latency mismatch between memory cells and the corresponding controller using typical delay elements is investigated and found to be highly variable for different Vdd values. A Speed Independent (SI) SRAM memory is then developed which can help avoid such mismatch problems. It can also be used to replace typical delay lines for use in bundled-data memory banks. A 1 Kb SI memory bank is implemented based on this method and analysed in terms of the latency and power consumption. In addition, a 1 Kb bundled-data memory bank using SI SRAM as delay bundling devices is also implemented. Comparative studies demonstrate the advantages and disadvantages of these methods.

Self-timed SRAM for Energy Harvesting Systems

Asynchronous communication mechanisms permit the implementation of data interfaces between heterogeneously timed entities at various hardware levels. A systematic approach to ACM classification, specification, and implementation facilitates their use in heterogeneously timed networks.

Delong Shang

Papers

Asynchronous system synthesis based on direct mapping using VHDL and Petri nets

Low-Cost Online Testing of Asynchronous Handshakes

High-security asynchronous circuit implementation of AES

Self-timed SRAM for Energy Harvesting Systems

Data communication in systems with heterogeneous timing