Inclusion of power electronics allows increased controllability and stability in power systems. The simulation of such systems on a large-scale is challenging due to the presence of a large number of switches and nonlinear devices. This paper presents an advanced simulation algorithm to solve the aforementioned problem. The algorithm considers separation of differential algebraic equations (DAEs) on the basis of numerical stiffness and applies hybrid discretization algorithms to simulate the DAEs. The DAEs, in this paper, represent the nonlinear nonautonomous switched system dynamics of power systems. Stability analysis is performed on a general class of nonlinear nonautonomous switched systems to show the constraints under which the proposed algorithm is stable. To show the validity of the proposed algorithm, two case studies are considered: 1) single high-voltage direct current (HVdc) substation based on the modular multilevel converter (MMC); and 2) an example three-terminal MMC-HVdc system. Relaxation techniques are introduced to create a stable interface for the separated DAEs. The developed algorithms are also validated with PSCAD/EMTDC-detailed reference models.

Numerical-Stiffness-Based Simulation of Mixed Transmission Systems

CORDIC algorithm is suitable to implement sine/cosine function, but the large number of iterations lead to great delay and overhead. Moreover, due to finite bit-width of operands and number of iterations, the relative error of floating-point sine or cosine is terrible when the input angle is close to 0 or $\pi /2$ , respectively. To overcome these shortcomings, TCORDIC algorithm, which combines low latency CORDIC and Taylor algorithm, is presented. After analyzing the latency of traditional CORDIC, low latency CORDIC is proposed, which adopts the technique of sign prediction, compressive iterations, and parallel iterations. Besides, the calculating boundary ( $N$ ), which is used for determining whether Taylor algorithm is selected or not in TCORDIC algorithm, is evaluated to achieve a trade-off between area and delay. Truncated multipliers are used to reduce the area further. Finally, Using TCORDIC algorithm, pipelined and iterative structures are implemented for IEEE-754 double precision floating-point sine/cosine with the input $Z\epsilon [0,\pi /2]$ . Under typical condition (1V, 25 °C), our designs are synthesized with 40 nm standard cell library. For a pipelined structure, the frequency is up to 1.70 GHz and area $194049.64~\mu {\mathrm { m}}^{2}$ . Frequency decreases to 1.45 GHz for iterative structure, but the area requires only $110590.81~\mu {\mathrm { m}}^{2}$ . TCORDIC is efficient in controlling relative error, and achieves the accuracy within one ulp (unit in the last place) for floating-point sine/cosine function.

Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm

Spaceborne synthetic aperture radar (SAR) plays an important role in many fields of national defense and the national economy, and the Fast Fourier Transform (FFT) processor is an important part of the spaceborne real-time SAR imaging system. How to meet the increasing demand for ultra-large-scale data processing and to reduce the scale of the hardware platform while ensuring real-time processing is a major problem for real-time processing of on-orbit SAR. To solve this problem, in this study, we propose a 128k-point fixed-point FFT processor based on Field-Programmable Gate Array (FPGA) with a four-channel Single-path Delay Feedback (SDF) structure. First, we combine the radix-23 and mixed-radix algorithms to propose a four-channel processor structure, to achieve high efficiency hardware resources and high real-time performance. Secondly, we adopt the SDF structure combined with the radix-23 algorithm to achieve efficient use of storage resources. Third, we propose a word length adjustment strategy to ensure the accuracy of calculations. The experimental results show that the relative error between the processor and the MATLAB calculation result is maintained at about 10−4, which has good calculation accuracy.

An FPGA-Based Four-Channel 128k-Point FFT Processor Suitable for Spaceborne SAR

Systems and methods relate to a division/root computation unit. A lookup table according to a Sweeney, Robertson, and Tocher (SRT) algorithm for a division/root computation is stored in a memory. Information related to a selected column corresponding to a divisor/root estimate is stored in a high-speed memory. Division/root computation is performed iteratively using the cached information to improve access times and reduce latency of accessing the entire lookup table on each iteration. In each iteration, a quotient/root is determined from the cached information based on a current partial remainder, and a next partial remainder is generated based on the quotient/root, the divisor/root estimate, and the current partial remainder.

High performance division and root computation unit

Application of a novel spatial non-reciprocal phase modulator in fiber optic gyroscope

Fast Fourier transform (FFT) accelerator and Coordinate rotation digital computer (CORDIC) algorithm play important roles in signal processing. We propose a configurable floating-point FFT accelerator based on CORDIC rotation, in which twiddle direction prediction is presented to reduce hardware cost and twiddle angles are generated in real time to save memory. To finish CORDIC rotation efficiently, a novel approach in which segmented-parallel iteration and compress iteration based on CSA are presented and redundant CORDIC is used to reduce the latency of each iteration. To prove the efficiency of our FFT accelerator, four FFT accelerators are prototyped into a FPGA chip to perform a batch-FFT. Experimental results show that our structure, which is composed of four butterfly units and finishes FFT with the size ranging from 64 to 8192 points, occupies 33230(3%) REGs and 143006(30%) LUTs. The clock frequency can reach 122MHz. The resources of double-precision FFT is only about 2.5 times of single-precision while the theoretical value is 4. What's more, only 13331 cycles are required to implement 8192-points double-precision FFT with four butterfly units in parallel.

Configurable Floating-Point FFT Accelerator on FPGA Based Multiple-Rotation CORDIC

The invention discloses a method and device for achieving a low delay basic transcendental function based on a mixed model CORDIC algorithm. The method comprises the following steps that the angle and function type in the floating point form in the IEEE-754 standard is input, format conversion and compressed mapping are conducted; rotating direction prediction is conducted on a Z data path according to a mapping angle and the function type; the X data path and the Y data path divide 64 iterations into the front 32 eight-level compressed iterations through a carry-save adder, four iterations are conducted for each level, and parallel computing is conducted on the last 32 iterations; format conversion is conducted a CORDIC iteration result according to the characteristics of the function. The device comprises a pre-processor, a mixed mode CORDIC computing module and a standardization processing module. The method has the advantages that the method is simple in structure, the circumference coordinate CORDIC algorithm and the hyperbolic coordinate CORDIC algorithm can be executed on the same hardware platform, delay is low, a period is short, speed is high, and precision is high.

Method and device for achieving low delay basic transcendental function based on mixed model CORDIC algorithmic

The invention discloses a method and device for achieving an SIMD structure floating point division in a general-purpose digital signal processor (GPDSP). The method comprises a first step of inputting two double precision floating point data or two groups of parallel SIMD double and single precision floating point data, adopting an SRT algorithm to perform division iterative computation and perform one-stage execution or multi-stage execution by truncation, executing repeated iterative computation in every stage, and enabling the times of iterative computation in every stage to be smaller than or equal to the maximum instruction cycle of the GPDSP; a second step of normalizing the mantissa of quotients according to data types and the number of stages executed in iterative computation, and obtaining a final quotient result after combination. The device comprises an iterative computation module corresponding to the method and a normalization processing module. The method and device for achieving the SIMD structure floating point division in the GPDSP can achieve double precision and SIMD double and single precision floating point division on identical hardware and have the advantages that the achieving method is simple, the application is flexible, hardware expenditure is small, the execution cycle is short, the delay is small, and division execution efficiency is high.

Method and device for achieving SIMD structure floating point division in general-purpose digital signal processor (GPDSP)

The invention discloses a method for achieving fixed point and floating point mixed division in a general-purpose digital signal processor (GPDSP). The method comprises a first step of inputting a divisor and a dividend, and if the divisor and the dividend are fixed point integers, shifting to execute a second step; if the divisor and the dividend are floating point data, shifting to execute a third step; the second step of enabling the divisor and the dividend to perform shifting according to a precursor zero number, calculating iteration times for executing division iterations, and executing iterations of a one-stage or multi-stage SRT algorithm according to fixed point data types and iteration times; performing shifting on a quotient result and obtaining a final quotient result, and obtaining a final remainder according to the final quotient result; a third step of working out mantissas of the divisor and the dividend, adopting the SRT algorithm to execute division iterative computation of the mantissas, and enabling the iterative computation to undergo one-stage execution or multi-stage execution by truncation; and normalizing the mantissas of the quotient result according to floating point data types and the number of stages executed in iterative computation. The achieving method has the advantages of being complete in division function, simple, short in execution cycle, small in time delay and high in division execution efficiency.

Method for achieving fixed point and floating point mixed division in general-purpose digital signal processor (GPDSP)

The invention discloses a method and device for achieving a low delay CORDIC trigonometric function based on a carry-save summator The method comprises the following steps of initializing an X data path, a Y data path and a Z data path; predicting the rotating direction of the Z data path, and outputting the rotating direction to the X data path and the Y data path, compressing the front N/2 circulation of the X data path and the Y data path into the N/8 level, and completing iteration for each level in one beat by adopting a carry-save adder; conducting parallel iteration on the last N/2 circulation of the X data path and the Y data path through the carry-save summator The device comprises an initialization module, a rotating direction predicting module, an iteration compressing module and a parallel iteration module, and the carry-save summator is adopted in both an iteration compressing unit and a parallel iteration unit The method and device have the advantages that hardware expenditure is small, a period is short, delay is short, throughput is large, and precision is high

Deng Ziye

Papers

Configurable Floating-Point FFT Accelerator on FPGA Based Multiple-Rotation CORDIC

Method and device for achieving low delay basic transcendental function based on mixed model CORDIC algorithmic

Method and device for achieving SIMD structure floating point division in general-purpose digital signal processor (GPDSP)

Method for achieving fixed point and floating point mixed division in general-purpose digital signal processor (GPDSP)

Method and device for achieving low delay CORDIC trigonometric function based on carry-save summator