Showing papers by "Derek J. Smith published in 1993"
Patent•
28 May 1993TL;DR: In this paper, an active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data, and a broadcast memory 22 is provided, which includes rows and column of storage location for holding control instructions.
Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data. A broadcast memory 22 is provided which includes rows and columns of storage locations for holding control instructions. Search circuitry 26, 52 is provided which is operable to receive at least one word of data from data memory 20 and test the word against a preselected search test condition. Control circuitry 24 is operable in response to control instructions received from the broadcast memory 22 to control the transfer of the word of data from the data memory 20 to the search circuitry 26, 52 and the test of the word by the search circuitry 26, 52.
57 citations
Patent•
28 May 1993TL;DR: In this paper, an active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results, and a broadcast memory 22 includes rows and column of storage location for holding control instructions.
Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.
56 citations
Patent•
28 May 1993TL;DR: In this paper, a memory system consisting of a processor and an active memory device coupled to a processor is described, where the active memory includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12.
Abstract: A memory system 10 is provided including a processor 12 and an active memory device 14 coupled to a processor 12. Active memory 14 includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12. Circuitry 26 is provided for identifying at least one active address from ones of the possible addresses stored in first memory 20 as a function of the actual address stored in second memory 22.
11 citations
Patent•
26 Aug 1993TL;DR: In this paper, the authors present an approach for storing all logic simulation signal values generated by a logic simulator during a simulation run, including a runtime array for storing a plurality of signal values for each time instance in a predetermined time period, and a checkpoint cache for selectively storing the plurality of signals stored in the runtime array at selected time instances.
Abstract: Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime array for storing a plurality of signal values for each time instance in a predetermined time period, and a checkpoint cache for selectively storing the plurality of signal values stored in the runtime array at selected time instances. A hyper-checkpoint array is further provided to checkpoint the signal values in the checkpoint cache. In addition, the time instances and values of memory writes are also checkpointed. A user may retrieve the value of any signal values generated during the simulation run and may additionally rewind the simulator to a user-specified time in the simulation run.
5 citations