In many important applications-such as search engines and relational database systems-data are stored in the form of arrays of integers. Encoding and, most importantly, decoding of these arrays consumes considerable CPUtime. Therefore, substantial effort has been made to reduce costs associated with compression and decompression. In particular, researchers have exploited the superscalar nature of modern processors and single-instruction, multiple-data SIMD instructions. Nevertheless, we introduce a novel vectorized scheme called SIMD-BP128i¾? that improves over previously proposed vectorized approaches. It is nearly twice as fast as the previously fastest schemes on desktop processors varint-G8IU and PFOR. At the same time, SIMD-BP128i¾? saves up to 2bits/int. For even better compression, we propose another new vectorized scheme SIMD-FastPFOR that has a compression ratio within 10% of a state-of-the-art scheme Simple-8b while being two times faster during decoding. Copyright © 2013 John Wiley & Sons, Ltd.

Decoding billions of integers per second through vectorization

Database community has made significant research efforts to optimize query processing on GPUs in the past few years. However, we can hardly find that GPUs have been truly adopted in major warehousing production systems. Preparing to merge GPUs to the warehousing systems, we have identified and addressed several critical issues in a three-dimensional study of warehousing queries on GPUs by varying query characteristics, software techniques, and GPU hardware configurations. We also propose an analytical model to understand and predict the query performance on GPUs. Based on our study, we present our performance insights for warehousing query execution on GPUs. The objective of our work is to provide a comprehensive guidance for GPU architects, software system designers, and database practitioners to narrow the speed gap between the GPU kernel execution (the fast mode) and data transfer to prepare GPU execution (the slow mode) for high performance in processing data warehousing queries. The GPU query engine developed in this work is open source to the public.

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The Yin and Yang of processing data warehousing queries on GPU devices

We present the first learned index that supports predecessor, range queries and updates within provably efficient time and space bounds in the worst case. In the (static) context of just predecessor and range queries these bounds turn out to be optimal. We call this learned index the Piecewise Geometric Model index (PGM-index). Its flexible design allows us to introduce three variants which are novel in the context of learned data structures. The first variant of the PGM-index is able to adapt itself to the distribution of the query operations, thus resulting in the first known distribution-aware learned index to date. The second variant exploits the repetitiveness possibly present at the level of the learned models that compose the PGM-index to further compress its succinct space footprint. The third one is a multicriteria variant of the PGM-index that efficiently auto-tunes itself in a few seconds over hundreds of millions of keys to satisfy space-time constraints which evolve over time across users, devices and applications.These theoretical achievements are supported by a large set of experimental results on known datasets which show that the fully-dynamic PGM-index improves the space occupancy of existing traditional and learned indexes by up to three orders of magnitude, while still achieving their same or even better query and update time efficiency. As an example, in the static setting of predecessor and range queries, the PGM-index matches the query performance of a cache-optimised static B+-tree within two orders of magnitude (83×) less space; whereas in the fully-dynamic setting, where insertions and deletions are allowed, the PGM-index improves the query and update time performance of a B+-tree by up to 71% within three orders of magnitude (1140×) less space.

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The PGM-index: a fully-dynamic compressed learned index with provable worst-case bounds

Index structures are one of the most important tools that DBAs leverage to improve the performance of analytics and transactional workloads. However, building several indexes over large datasets can often become prohibitive and consume valuable system resources. In fact, a recent study showed that indexes created as part of the TPC-C benchmark can account for 55% of the total memory available in a modern DBMS. This overhead consumes valuable and expensive main memory, and limits the amount of space available to store new data or process existing data. In this paper, we present a novel data-aware index structure called FITing-Tree which approximates an index using piece-wise linear functions with a bounded error specified at construction time. This error knob provides a tunable parameter that allows a DBA to FIT an index to a dataset and workload by being able to balance lookup performance and space consumption. To navigate this tradeoff, we provide a cost model that helps determine an appropriate error parameter given either (1) a lookup latency requirement (e.g., 500ns) or (2) a storage budget (e.g., 100MB). Using a variety of real-world datasets, we show that our index is able to provide performance that is comparable to full index structures while reducing the storage footprint by orders of magnitude.

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FITing-Tree: A Data-aware Index Structure

Stream compaction is a common parallel primitive used to remove unwanted elements in sparse data. This allows highly parallel algorithms to maintain performance over several processing steps and reduces overall memory usage. For wide SIMD many-core architectures, we present a novel stream compaction algorithm and explore several variations thereof. Our algorithm is designed to maximize concurrent execution, with minimal use of synchronization. Bandwidth and auxiliary storage requirements are reduced significantly, which allows for substantially better performance. We have tested our algorithms using CUDA on a PC with an NVIDIA GeForce GTX280 GPU. On this hardware, our reference implementation provides a 3× speedup over previous published algorithms. Copyright

Efficient stream compaction on wide SIMD many-core architectures

Major web search engines answer thousands of queries per second requesting information about billions of web pages. The data sizes and query loads are growing at an exponential rate. To manage the heavy workload, we consider techniques for utilizing a Graphics Processing Unit (GPU). We investigate new approaches to improve two important operations of search engines -- lists intersection and index compression.For lists intersection, we develop techniques for efficient implementation of the binary search algorithm for parallel computation. We inspect some representative real-world datasets and find that a sufficiently long inverted list has an overall linear rate of increase. Based on this observation, we propose Linear Regression and Hash Segmentation techniques for contracting the search range. For index compression, the traditional d-gap based compression schemata are not well-suited for parallel computation, so we propose a Linear Regression Compression schema which has an inherent parallel structure. We further discuss how to efficiently intersect the compressed lists on a GPU. Our experimental results show significant improvements in the query processing throughput on several datasets.

/pdf/efficient-parallel-lists-intersection-and-index-compression-7evuuk23tg.pdf

Efficient parallel lists intersection and index compression algorithms using graphics processing units

Lists intersection is an important operation in modern web search engines. Many prior studies have focused on the single-core or multi-core CPU platform or many-core GPU. In this paper, we propose a CPU-GPU cooperative model that can integrate the computing power of CPU and GPU to perform lists intersection more efficiently. In the so-called synchronous mode, queries are grouped into batches and processed by GPU for high throughput. We design a query-parallel GPU algorithm based on an element-thread mapping strategy for load balancing. In the traditional asynchronous model, queries are processed one-by-one by CPU or GPU to gain perfect response time. We design an online scheduling algorithm to determine whether CPU or GPU processes the query faster. Regression analysis on a huge number of experimental results concludes a regression formula as the scheduling metric. We perform exhaustive experiments on our new approaches. Experimental results on the TREC Gov and Baidu datasets show that our approaches can improve the performance of the lists intersection significantly.

Efficient lists intersection by CPU-GPU cooperative computing

Intersection of inverted lists is a frequently used operation in search engine systems. Efficient CPU and GPU intersection algorithms for large problem size are well studied. We propose an efficient GPU algorithm for high performance intersection of inverted index lists on CUDA platform. This algorithm feeds queries to GPU in batches, thus can take full advantage of GPU processor cores even if problem size is small. We also propose an input preprocessing method which alleviate load imbalance effectively. Our experimental results based on a real world test set show that the batched algorithm is much faster than the fastest CPU algorithm and plain GPU algorithm.

A Batched GPU Algorithm for Set Intersection

Intersection of sorted inverted lists is an important operation in the web search engines. Various algorithms to improve the performance of this operation have been introduced in the literature [1, 3, 5]. Previous research works mainly focused on single-core or multi-core CPU platform and did not consider the query traffic problem arises in the actual systems. Modern graphics processing units (GPUs) give a new way to solve the problem. Wu et al. [6] presented a CPU-GPU cooperative model which can dynamically switch between the asynchronous mode and the synchronous mode. Under light query traffic, asynchronous mode is triggered, each newly arriving query is serviced by an independent thread. Under heavy query traffic, synchronous mode is triggered, all active threads are blocked and a single thread takes control of query processing. Queries are grouped into batches at CPU end, and each batch is processed by GPU threads in parallel. We summarize that putting the operations on GPU has two advantages: The massive on-chip parallelism of GPU may greatly reduce the processing time of lists intersection; A great part of work on CPU is offloaded to GPU. Overall the GPU will significantly increase throughput and reduce average response time in the synchronous mode. In this paper we consider techniques for improving the performance of the GPU batched algorithm proposed in [6] assuming sufficient queries at the CPU end.

Fast lists intersection with Bloom filter using graphics processing units

The invention discloses a reverse index intersection method which comprises the following steps of: pre-processing; drawing a two-dimensional scatter diagram by taking the index of docID as a transverse coordinate and the value of the docID as a longitudinal coordinate; generating a linear regression straight line based on a least square method to ensure that the sum of squares of vertical deviations among all points in a figure and the straight line is minimized; evaluating a left safe search range and a right safe search range; and storing evaluated linear regression information. During reverse index intersection, the safe search range of the docID to be searched in a reverse list is determined according to the stored linear regression information of the reverse list, and a certain existing search method is adopted to search in the range. By adopting the reverse index intersection method disclosed by the invention, the search range can be reduced, the search time can be shortened, the response time of a search engine can be shortened, and the user experience can be enhanced.

Di Wu

Papers

Efficient parallel lists intersection and index compression algorithms using graphics processing units

Efficient lists intersection by CPU-GPU cooperative computing

A Batched GPU Algorithm for Set Intersection

Fast lists intersection with Bloom filter using graphics processing units

Reverse index intersection method