An embodiment of the invention in a quad flat no-lead package is described. The package is produced by encapsulating an integrated circuit chip, a die pad to which the chip is affixed, and leads which are connected to the chip in a molding compound. Leads are positioned on all four sides of the package, the exposed (bottom) portions of the leads are coplanar with the bottom of the package, and the leads do not extend, or extend only slightly, beyond the area of the package. The package includes a die pad also having an exposed (bottom) portion that is coplanar with the bottom of the package. The top portions of the leads are coplanar with the top surface of the die pad, and are flat.

Leadframe based chip scale package and method of producing the same

The present invention provides an encapsulation method and apparatus that allows high throughput production of reliable, high quality board-on-chip packages, or other semiconductor die packages, from a multi-chip array arrangement on a carrier substrate. In an exemplary embodiment relating to a board-on-chip array, a mold is provided with an upper mold platen and a plurality of upper mold platen cavities for encapsulating wire bonds and related interconnections on a first side of a multi-chip carrier substrate. The mold further includes a lower mold platen and a lower mold platen cavity for encapsulating substantially the entire second side of the carrier substrate, to include a plurality IC chips mounted thereon in array fashion. Substrate support elements, in the form of standoffs pins or bosses, are provided for supporting the multi-chip carrier substrate during the encapsulation process. The standoff pins or bosses are configured to contact, or nearly contact, the die side area of the multi-chip carrier substrate to prevent or minimize substrate deflection during the fill of the mold cavities with encapsulant material. The standoff pins or bosses may be integral to a mold cavity or may be removable. The standoff pins or bosses may further be aligned along edges of lines representing a series of individual device packages. A singulation saw may be used to cut along marks left in the encapsulation to define individual device packages. The individual packages formed by the methods of the present invention may be used to construct a semiconductor device assembly.

Method and apparatus for encapsulating a multi-chip substrate array

A semiconductor device packaged in a plastic package wherein the thickness of the plastic mold on the top surface of the semiconductor device chip is less than the height of the lead on the top surface of the semiconductor device chip and the top surface to the plastic mold filling the space between the leads is convex downward in an arc shape, and a metal mold employable for producing the semiconductor device packaged in a plastic package comprising a lower mold having a cavity in which a semiconductor device chip provided with a plurality of leads thereon, is placed during a molding process, and an upper mold having a lower surface having a plurality of longitudinal projections and recesses arranged in parallel to one anther, the cross section of the longitudinal projections and recesses produced along the lower surface of the upper mold being effective to cause longitudinal linear contact along the longitudinal projections and recesses, between the lower surface and the edges of the leads, during a molding process.

Semiconductor device packaged in plastic and mold employable for production thereof

A semiconductor device which reduces and simultaneously achieves a uniform mounting height, does not require complicated steps for mounting individual chips, improves the manufacturing yield, achieves a uniform height of the semiconductor device without being affected by the variation in thickness of the chips, and enables execution of electrical tests all together and a process for production of the same, wherein a semiconductor chip is housed, with its active surface facing upward, in a through hole of a printed circuit board provided with an interconnection pattern on its top surface, electrode terminals of the active surface are connected to the interconnection pattern by bonding wires, a sealing resin layer seals the bonding wires and semiconductor chip together and fixes the semiconductor chip in the through hole, and the bottom surface of the printed circuit board, the downward facing back surface of the semiconductor chip, and the bottom surface of the sealing resin layer are finished to the same flat surface by grinding and polishing.

Resin sealed stacked semiconductor packages with flat surfaces

A ball grid array (BGA) semiconductor package includes a paddle, a semiconductor chip on the paddle, a plurality of first leads around a periphery of the paddle, a plurality of second leads attached to a lower surface of each of the first leads, a plurality of conductive wires electrically connecting the semiconductor chip and the first leads, a molding unit sealing the paddle, the semiconductor chip, the first leads, the second leads, and the conductive wires, except for a lower portion of the second leads, and a plurality of solder balls attached to the lower portion of the second leads. A method of fabricating a ball grid array (BGA) semiconductor package having first and second frames includes the steps of attaching a semiconductor chip to a paddle located on the first frame, electrically connecting a plurality of first leads to the semiconductor chip, electrically connecting a plurality of second leads to the plurality of first leads, aligning a first junction unit of the first frame with a second junction unit of the second frame, attaching the first frame to the second frame, molding the first and second frames, and attaching a plurality of solder balls to each of the plurality of second leads.

Ball grid array semiconductor package comprised of two lead frames

PROBLEM TO BE SOLVED: To prevent paddle from inclining at a molding step by providing a first supporting leg which supports the paddle by bending a rim part of the paddle and a second supporting leg which supports tie bars by bending both sides of a rim part of at least one tie bar among a plurality of tie bars. SOLUTION: A paddle 13 which is formed at the central part of a rail 11 and a semiconductor chip 4 is mounted thereon and four tie bard 15a, 15b, 15c and 15d which support the paddle 13 as to locate at the inside of the rail 11 are provided. Also leads 6 at which terminal parts pad surfaces for wire bonding is located and with which base terminals the rail 11 is junctioned are provided. Especially first and second supporting legs 9 and 10 are provided. The first supporting leg 9 supports the paddle 13 by bending a rim part of the paddle 13. The second supporting leg 10 supports the tie bars 15a to 15d by bending both sides of a rim part of at least one tie bar of the tie bars 15a to 15d. Thus, the paddle 13 can be kept not to be inclined by pressure of epoxy resin for molding during a molding step.

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Papers

Lead frame and semiconductor package

ドン キム スン

Papers

Lead frame and semiconductor package

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