A semiconductor non-volatile optical memory device is constructed by providing light-permeable charge retention means in an insulating layer on a first semiconductor surface into which photo-generated carriers in the surface of the first semiconductor region are injected over the semiconductor-insulator potential barrier by applying reverse bias between the first semiconductor region and a second region forming a rectifying junction with the first semiconductor region. Also disclosed in a non-volatile memory integrated circuit employing one or more of said devices together with light source in the same package. The non-volatile memory integrated circuit operates under low bias voltage and is compatible with a high speed integrated logic circuits.

Semi-conductor non-volatile optical memory device

A dynamic memory storage cell requires only one field effect transistor to store binary data The data is represented in the form of stored charge utilizing the inherent metal-insulatorsemiconductor capacitance and P-N junction capacitance at the source node of the field-effect transistor An extended portion of the source diffusion in combination with overlying thin oxide and metal layers form a capacitor that further enhances charge storage A matrix of the memory cells form an extremely high density random access memory

One transistor dynamic memory cell

A TTL compatible erasable programmable read-only memory (PROM) which uses a single n-channel device having a floating gate for each memory cell. The entire memory including the periphery circuits, are disposed on a silicon substrate. Only a single externally generated high voltage input or "pin" is required for programming.

Erasable programmable read-only memory

A programmable analog transversal filter is disclosed for processing analog signals and comprising a charge-coupled device (CCD) for receiving a series of discrete analog signals to be delayed by increasing periods and applied to the outputs of the CCD, and a plurality of MNOS memory devices coupled to the taps of the CCD and programmed so that the output of a CCD tap is multiplied by a particular factor. In turn, the outputs of the MNOS memory devices are summed to provide an output signal ##EQU1## where W k is the weighting factor associated the k th MNOS memory device. The weighting factors are set into the system by varying the threshold voltage of the corresponding MNOS device. Positive and negative weighting factors are implemented by using first and second MNOS memory elements for each tap of the CCD, whereby depending upon the program incorporated into the system, one of the first and second MNOS memory devices is programmed to give either a positive weighting factor and the other MNOS memory device a negative weighting factor. Further, a reiterative method of setting the weights into the MNOS memory device is used to compare the system output indicative of the weighting factor as set into the MNOS memory devices, with the desired weighting factor as stored in a suitable storage memory such as a ROM, whereby a correction signal is developed to adjust the threshold voltage V Th of the MNOS memory device in accordance with the stored weighting factor. In one illustrative embodiment, the weighting factors are set in accordance with sinusoidal signals, whereby the system performs a filtering function to provide an output upon receipt of an input signal of desired frequency. In addition, the MNOS devices are reprogrammable, thus permitting a single such system to be used in many different applications. In this regard, this system is particularly adapted for complex signal processing including filtering, generating desired functions, synthetic aperture radar signal processing and target identification processing.

Programmable analog transversal filter

A programmable analog transversal filter is disclosed for processing analog signals and comprising a charge-coupled device (CCD) for receiving a series of discrete analog signals to be delayed by increasing periods and applied to the outputs of the CCD, and a plurality of MNOS memory devices coupled to the taps of the CCD and being programmed so that the output of a CCD tap is multiplied by a particlar factor In particular, the MNOS memory devices are disposed in a matrix of rows and columns The outputs of the MNOS memory devices of each row are summed and the row output signal e(t- ##EQU1## WHERE W k is the weighting factor associated with the K th MNOS memory device are applied to corresponding inputs of a parallel-to-series converter taking the form of a CCD The parallel-to-series converter then is enabled to serially read out the row outputs The weighting factors are set into the system by varying the threshold voltage of the corresponding MNOS device Positive and negative weighting factors are implemented by using first and second MNOS memory elements for each tap of the CCD, whereby depending upon the program incorporated into the system, one of the first and second MNOS memory devices is programmed to give a positive weighting factor and the other memory device a negative weighting factor Further, a reiterative method of setting the weights into the MNOS device is used to compare the system output indicative of the weighting factor as set into one of the MNOS memory devices with the desired weighting factor as stored in a suitable storage memory such as a ROM, whereby a correction signal is developed to adjust the threshold voltage V Th of the one MNOS memory device in accordance with the stored weighting factor In one illustrative embodiment, the weighting factors are set in accordance with sinusoidal signals, whereby the system performs a filtering function to provide an output upon receipt of an input signal of desired frequency In addition, the MNOS devices are reprogrammable, thus permitting a single such system to be used in many different applications In this regard, this system is particularly adapted for complex signal processing including filtering, generating desired functions, synthetic aperture radar signal processing and target identification processing

Discrete analog processing system including a matrix of memory elements

A semiconductor memory array consists of an array of MNOS transistors. Each transistor possesses an hystereris relationship between the gate voltage required to turn on the transistor and a previously applied gate voltage. Thus each MNOS transistor stores, by itself, one bit of information. A binary "1" is written into a transistor by applying a voltage of a first selected magnitude to the gate of the MNOS transistor while grounding its source and drain. Applying simultaneously a negative voltage to the drain of the MNOS transistor lowers the voltage across the dielectric beneath the MNOS transistor's gate electrode and prevents the storage of a binary "1." No electrical isolation is required between the MNOS transistors.

Dov Frohman-Bentchkowsky

Papers

Integrated mnos memory organization