Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

Fused voltage level shifting latch

The invention discloses a PTP network time online monitoring module. The device consists of a digital signal processing part, an Ethernet interface chip, a power supply chip and a crystal oscillator,and is internally provided with an embedded operating system and embedded software. According to the invention, a timing signal of a Beidou satellite system can be received, an internal clock of equipment is synchronized, and a PTP time synchronization protocol is realized through an embedded operating system and embedded software, so as to realize online monitoring of an in-network PTP main clock.

PTP network time online monitoring module

A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

Method and apparatus for multi-voltage domain sequential elements

Multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ICs) and related methods are disclosed. A flip-flop circuit latches a representation of a received input data signal in a lower voltage domain, in a latch circuit in a higher voltage domain without need for separate voltage level shifters. As a result, insertion loss/delay is minimized, thereby increasing performance. In certain aspects, the flip-flop circuits employ a gate-controlled, data control transistor to control activation of the latch circuit. By coupling the input data signal to a gate of the data control transistor, the input data signal in the lower voltage domain is not directly latched into the latch circuit. Instead, the data control transistor is configured to activate the latch circuit to latch a voltage in the higher voltage domain representing a logic value of the input data signal in the lower voltage domain in response to a clock signal.

Du Yang

Papers

MULTI-LEVEL CONVERSION FLIP-FLOP CIRCUITS FOR MULTI-POWER DOMAIN INTEGRATED CIRCUITS (ICs) AND RELATED METHODS