In the recent past, there has been an evolution in wireless communications toward multifunctions and multistandard mobile terminals. Reducing the number of external components to a minimum is key when the same mobile terminal has to process several different standards. Highly integrated solutions in low-cost silicon technologies are thus required. Zero-IF and low-IF receiver architectures are most suitable for a high level of integration. This paper presents a review of global system for mobile communications, universal mobile telecommunication system, Bluetooth, and wireless local area network (IEEE802.11a, b, g and HiperLAN2) standards, likely to all be present in the "universal" terminal of the future, enabling global roaming and wireless connectivity. The various standards are analyzed in order to find the optimal architecture and the building-block specifications for the receive section, with particular care to the RF front-end. State-of-the-art solutions are discussed, with emphasis on direct conversion CMOS implementations. A multistandard architecture for a fully-integrated CMOS receiver is proposed.

Toward multistandard mobile terminals - fully integrated receivers requirements and architectures

A single-chip 2.4-GHz CMOS radio transceiver with integrated baseband processing according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high sensitivity and low power consumption, and achieves -101 dBm sensitivity for 1% packet error rate. The transmitter topology is based on a PLL direct-modulation scheme. Optimizations of architecture and circuit design level in order to reduce the transceiver power consumption are described. Special attention is paid to the RF front-end design which consumes 2.4mA in receive mode and features bidirectional RF pins. The 5.77 mm2 chip is implemented in a standard 0.18-mum CMOS technology. The transmitter delivers +3 dBm into the 100-Omega differential antenna port

A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications

Transceiver architecture selection: Review, state-of-the-art survey and case study

This paper presents a CMOS RF amplitude detector as a practical integrated test device and demonstrates its application for on-chip testing. The proposed circuit performs full-wave rectification and generates a dc voltage proportional to the amplitude of an RF signal over a wide frequency range. The design considerations and analysis of operation for the employed class-AB rectifier are described. Fabricated in a standard 0.35-mum CMOS process, the RF detector uses only 0.031 of area and presents an equivalent input capacitance of 13 fF. Measurements show that this RF test device has a detection dynamic range of 30 dB from 900 MHz to 2.4 GHz. Experimental results for the application of the RF amplitude detector in the built-in measurement of the gain and compression of a 1.6-GHz low-noise amplifier fabricated in the same chip are also presented.

A Broadband CMOS Amplitude Detector for On-Chip RF Measurements

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

A single-chip Bluetooth transceiver in 018/spl mu/m CMOS integrates a direct VCO modulation transmitter and 15MHz-IF receiver to reduce power consumption and cost The receiver achieves a sensitivity of -77dBm and transmitting power of +4dBm

Duc Minh Nguyen

Papers

A single-chip CMOS Bluetooth transceiver with 1.5MHz IF and direct modulation transmitter