It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

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High-speed CMOS circuit technique

An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm2 test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 σ/μ), 567 fJ (0.037 σ/μ), and 730 kHz (0.184 σ/μ), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

This paper reports on a novel high-density CMOS-based silicon microprobe array for intracortical recording applications. In contrast to existing systems, CMOS multiplexing units are integrated directly on the slender, needle-like probe shafts. Single-shaft probes and four-shaft combs have been realized with 188 and 752 electrodes, respectively, with a pitch of 40 μm arranged in two columns along 4-mm-long probe shafts. Rather than performing a mechanical translation of the probe shaft relative to the brain tissue to optimize the distance between electrodes and neurons, the electrode position is adjusted by electronically switching between the different electrodes along the shaft. The paper presents the probe concept, the CMOS circuitry design, the applied post-CMOS fabrication process, and the assembled probe systems.

CMOS-Based High-Density Silicon Microprobe Arrays for Electronic Depth Control in Intracortical Neural Recording

In this paper we show that, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay minimization is worthwhile to improve the performance in high-speed designs In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path Simulations are performed on several well-known TGMS FFs, designed in a 65-nm technology, to validate the correctness of such a procedure and of the underlying assumptions Significant improvements are found on delay and, remarkably, on energy and area occupation, thus showing that this approach allows to correctly deal with the actual path effort in such circuits and hence to more properly steer the design towards the achievement of energy efficiency in the high-speed region

Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops

A novel low-power nonvolatile magnetic flip-flop is introduced in this paper. The perpendicular magnetic anisotropy spin torque transfer magnetic tunnel junction (STT-MTJ) is used to design the hybrid MTJ/CMOS circuit, which is implemented with 28-nm high-κ metal gate and planar ultrathin body and buried oxide fully depleted silicon on insulator technology. The proposed flip-flop structure named SA-MFF shares a sensing amplifier for normal flip-flop mode and nonvolatile data sensing mode. The modified latch at output stage improves flip-flop latency. The proposed SA-MFF is symmetrical, which provides an equal delay for both true and complementary outputs. It can strengthen weak input signals (minimum 300 mV) and latch them to supply voltage. Forward body biasing transistors allow for fast operation and minimum energy consumption across all modes. The proposed SA-MFF achieves 45.2-ps latency, 50.1-ps clock to output delay, 12.71 μW active power and 343.6 nW of leakage power with 1-V supply voltage, and 6.47-μm × 4.54 μm layout area. Moreover, reliability issues are highlighted with reliability-aware simulations. Process variations of transistors/MTJs and stochastic characteristics of MTJs are investigated. Clock jitter effect and flip-flop metastability are studied.

Dutch Patent

Papers

Clocked CMOS Calculator Circuitry