This paper characterizes the potentially catastrophic effect of crosstalk glitches on representative circuit implementations of two widely used asynchronous protocols. It is demonstrated that the crosstalk glitches can induce false events, which can undesirably propagate into asynchronous interface circuits and may cause system failure. Conventionally, to a circuit designer, glitch propagation (GP) due to aggressor-to-quiet-line crosstalk (AQX) in asynchronous handshake schemes can only be observed through circuit-level analysis/simulation. In this paper, circuit-level analysis is first performed to prove that even optimized conventional asynchronous circuits allow crosstalk glitches produced over moderate-length interconnects (1.5 mm) to propagate. This is a precursor to a more problematic crosstalk glitch occurrence due to further scaling of technologies. To warn the digital designers from GP due to AQX, a novel modeling technique is proposed. This modeling method works at the logic level to facilitate asserting asynchronous interface robustness to crosstalk glitches. This model can accurately identify the possibility of intrinsic (to the asynchronous interface) crosstalk GP in asynchronous circuits at the logic level and, hence, provides a foundation to formally verify such circuits. To our knowledge, this is the first work on modeling GP due to AQX at the logic level for asynchronous circuits.

Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems

The authors propose an asynchronous-logic (async) quasi-delay-insensitive (QDI) autonomous signal-validity half-buffer (ASVHB) realisation approach for low power sub-threshold operation (V DD = 0.2 V). There are three key attributes in the proposed ASVHB realisation approach. First, the ASVHB realisation approach embodies integrated autonomous validity signals, which are unique and are used exclusively to simplify the circuit implementation for QDI protocol. Second, the ASVHB realisation approach applies the fine-grained gate-level method, which propagates data through a single-cell datapath pipeline to maximise the throughput rate. Third, the ASVHB realisation approach adopts the static-logic implementation, which maintain stable output states (by connecting them directly to the power rails), to feature high robustness for sub-threshold operation. They compare their ASVHB realisation approach against the competitive reported weak-conditioned half-buffer (WCHB) and pre-charged half-buffer (PCHB) realisation approaches. The WCHB and PCHB library cells, on average, require ∼2.1 × and ∼1.9 × more transistors than the ASVHB library cells. With respect to a 3-stage pipeline realisation, the WCHB and PCHB pipelines, on average, require 1.8 × and 1.5× more transitions per-cycle than the ASVHB pipeline. They design an async 32-bit arithmetic and logic unit (ALU) based on the proposed ASVHB realisation approach (at 65 nm CMOS process). Their ASVHB ALU occupies 0.092 mm2, and in many merits, outperforms the WCHB and PCHB counterparts. The WCHB and PCHB counterparts require ∼1.7 × and ∼1.4× more transistors, respectively, than their design. At the sub-threshold voltage of V DD = 0.2 V, the WCHB and PCHB counterparts dissipate ∼1.7× and ∼2.6× more energy, respectively, and are, respectively, ∼0.95× and ∼0.73× slower throughput.

Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer

This paper presents a Fixed Priority Arbiter (FPA) which fully takes benefice of asynchronous design. It signs up in a Time Correlated Single Photon Counting system where the data transfer from the Time to Digital Converters to the readout or process unit is a critical aspect. In order to increase the photon counting rate of the setup, the device has to handle a large amount of data following the increasing number of sensors. Thanks to its asynchronous design, the proposed FPA can be easily assembled to build a wide data path tree to guide all the data to a single output. The implementation on a 180 nm CMOS technology shows that a 128 input wide path tree can achieve a burst input rate of 21 Giga event per second while sustaining an output data rate of 333 Mega event per second.

An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems

Miniaturization of integrated circuits (ICs) due to the improvement in lithographic techniques in modem deep sub-micron (DSM) technologies allows several complex processing elements to coexist in one IC, which are called System-on-Chip. As a first contribution, this thesis quantitatively analyzes the severity of timing constraints associated with Clock Distribution Network (CDN) in modem DSM technologies and shows that different processing elements may work in different dock domains to alleviate these constraints. Such systems are known as Globally Asynchronous Locally Synchronous (GALS) systems. It is imperative that different processing elements of a GALS system need to communicate with each other through some interfacing technique, and these interfaces can be asynchronous or synchronous. Conventionally, the asynchronous interfaces are described at the Register Transfer Logic (RTL) or system level. Such designs are susceptible to certain design constraints that cannot be addressed at higher abstraction levels; crosstalk glitch is one such constraint. This thesis initially identifies, using an analytical model, the possibility of asynchronous interface malfunction due to crosstalk glitch propagation. Next, we characterize crosstalk glitch propagation under normal operating conditions for two different classes of asynchronous protocols, namely bundled data protocol based and delay insensitive asynchronous designs. Subsequently, we propose a logic abstraction level modeling technique, which provides a framework to the designer to verify the asynchronous protocols against crosstalk glitches. The utility of this modeling technique is demonstrated experimentally on a Xilinx Virtex-II Pro FPGA. Furthermore, a novel methodology is proposed to quench such crosstalk glitch propagation through gating the asynchronous interface from sending the signal during potential glitch vulnerable instances. This methodology is termed as crosstalk glitch gating. This technique is successfully applied to obtain crosstalk glitch quenching in the representative interfaces. This thesis also addresses the dock skew challenges faced by high-performance synchronous interfacing methodologies in modem DSM technologies. The proposed methodology allows communicating modules to run at a frequency that is independent of the dock skew. Leveraging a novel clock-scheduling algorithm, our technique permits a faster module to communicate safely with a slower module without slowing down. Safe data communications for mesochronous schemes and for the cases when communicating modules have dock frequency ratios of integer or coprime numbers are theoretically explained and experimentally demonstrated. A clock-scheduling technique to dynamically accommodate phase variations is also proposed. These methods are implemented to the Xilinx Virtex II Pro technology. Experiments prove that the proposed interfacing scheme allows modules to communicate data safely, for mesochronous schemes, at 350 MHz, which is the limit of the technology used, under a dock skew of more than twice the time period (i.e. a dock skew of 12 ns)

Inter-module Interfacing techniques for SoCs with multiple clock domains to address challenges in modern deep sub-micron technologies

This paper proposes a novel solution to make asynchronous handshake interfaces tolerant to crosstalk-glitch propagation (GP). This study leverages our recently proposed crosstalk-glitch modeling technique for asynchronous systems, which models the crosstalk GP in asynchronous interfaces. In this paper, a novel set of solutions to quench the GP is proposed. This set of solutions is called crosstalk-glitch gating, as the quenching is obtained by using carefully generated control signals. A step-by-step method is recommended to apply crosstalk-glitch gating to conventional asynchronous handshake interfaces. Transistor-level electrical simulations demonstrate that our method effectively generates crosstalk-glitch gate-controlling signals. In comparison with contemporary signal-integrity management techniques, our gating methodology can be applied to fewer nodes and earlier in the design cycle.

Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems

In SoC design, synchronous buses are used frequently to interconnect several IPs. However, it is difficult to use synchronous buses for SoC design because of the increase of wire delay caused by the crosstalk effect and the difficulty of synchronisation caused by the clock-skew problem. The use of an asynchronous bus is an alternative solution for SoC design methodology. A new handshake protocol is proposed using the return-to-zero data encoding scheme for the implementation of a new high performance asynchronous bus. Simulation results reveal that the proposed handshake protocol increases the read throughput of the asynchronous bus by 30.5%, and decreases the read latency by 12.5%.

E.-G. Jung

Papers

Handshake protocol using return-to-zero data encoding for high performance asynchronous bus