A method for testing at least one logic block of a processor (12) includes, during execution of a user application by the processor, the processor generating a stop and test indicator (24). In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

Method and apparatus for testing a data processing system

A plurality of test points are located at predetermined circuit nodes in a processing system. Test code which includes a set of software-controllable interrupts is executed using a multiple input shift register (MISR) to generate a MISR signature. One or more selected software-controllable interrupt types are determined. During execution of the test code, the MISR is used to also accumulate data values from the plurality of test points during exception processing of one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types to generate the MISR signature. A test control register has a plurality of fields, each for selecting or not selecting a corresponding software-controllable interrupt type.

Selective MISR data accumulation during exception processing

A data processing system (10) implements state machine (82) and register logic (80) such that no external control or data is required during execution of a dual scan path test operation. Prior to execution of the dual scan path test operation, a user of data processing system (10) initializes a system with a plurality of values which will be used during execution of the dual scan path test operation. After initialization, data processing system (10) executes the dual scan path test operation automatically and requires no additional information from the user.

Method and apparatus for performing dual scan path testing of an array in a data processing system

A method and apparatus for scan testing an array (20) in a data processing system (10). In one form, the present invention uses a scanning sense amplifier (22x) which can perform the three functions of a sense amplifier, a master test latch for scan testing, and a slave test latch for scan testing. Using one scanning sense amplifier (22x) to perform all three functions reduces the amount of circuitry required to scan test an array (20). The same stimulus is applied twice to the array (20); and half of the output data bits are scanned out during each application of the stimulus. One extra output data bit is also scanned out during each application of the stimulus. The end result is a reduction in the circuitry required to perform scan testing.

Method and apparatus for scan testing an array in a data processing system

The field of test engineering for very large scale integrated (VLSI) circuits is inundated with requirements to improve test coverage, reduce overhead and decrease development time. In response to this is a design methodology that will eliminate the test generation effort. This will reduce overall production costs, and provide a savings for products manufactured in low volumes. The approach utilizes known methods of partitioning circuits into smaller portions. Each portion being fully testable, the entire circuit is fully testable, neglecting portions of the Built-In-Self-Test (BIST) circuit itself. Overall, the results show that for small volume production, this methodology could be the best available option for a large class of circuits. Furthermore, it also provides a high degree of reliability in terms of the quality of the manufacturing test, and does not require expensive test devices, such as high-speed wafer-probe testers. The new design cycle that is presented eliminates time for test generation in lieu of approximately fifteen-percent impact in performance and size. >

Improving the testability of VLSI circuits through partitioning

The purpose of this paper is to describe the testability features implemented in Motorola's recently completed design of a sixteen bit microcontroller, the 68HC16Z1. The discussion includes a brief introduction to the 68HC16Z1, test objectives and organization along with descriptions of design for test (DR) techniques and structures.

E. Hoang

Papers

Testability features of the 68hc16z1