An efficient partial scan technique called Ballast (balanced structure scant test) is presented. Scan path storage elements (SPSEs) are selected such that the remainder of the circuit has certain desirable testability properties. A complete test set is obtained using combinatorial automatic test pattern generation (ATPG). Some SPSEs may need to be provided with a HOLD mode; their number is minimized by ordering the registers in the scan path and formatting the test patterns appropriately. This methodology leads to a low area overhead and allows 100% coverage of irredundant faults. >

The Ballast methodology for structured partial scan design

In the proposed partial scan methodology, the scan path is constructed so that the rest of the circuit belongs to a class of circuits called balanced sequential structures. Test patterns for this structure are generated by treating it as being combinational. Each test pattern is applied to the circuit by shifting it into the scan path. holding it constant for a fixed number of clock cycles, loading the test result into the scan path, and then shifting it out. This technique achieves full coverage of all detectable faults with a minimal number of scannable storage elements and using only combinational test pattern generation. >

BALLAST: a methodology for partial scan design

This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfer (RT) level which reflects test pattern generation costs, fault coverage and test application time. The testability is measured by controllability and observability, and determined by the structure of a design, the depth from I/O ports and the functional units used. In our approach, hardto-test parts are detected by a testability analysis algorithm and transformed by some known DFT techniques. Our experimental results show that testability improvement transformations guided by the RT level testability analysis have a strong correlation to ATPG results at gate level.

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1994/eurdac94/pdffiles/v09_3.pdf

Testability analysis and improvement from VHDL behavioral specifications

Register-transfer level designs that are derived from high-level synthesis systems generally consist of functional blocks and registers that are interconnected by multiplexers and buses to maximize resource sharing These multiplexer and bus structures have the unique ability to behave asswitches, i.e., to logically partition the circuit when their control inputs are manipulated in different ways. The presence of switches, the selection of scan registers can be influenced. This leads to an efficient partial scan methodology presented in this paper. Second, switches help set up data transfer paths calledI-paths. By employingI-paths to transport test data, the functional logic in the circuit can be separated from the switching logic for the purpose of test generation. This can lead to a reduction in test generation costs for a partial scan design. Thus the techniques presented in this paper help to minimize both testability overhead and test generation cost in bus-based circuits. This methodology is implemented in the SIESTA system for serial scan design.

Partial scan design of register-transfer level circuits

ATWIG is a heuristic automatic test pattern generator (ATG) which employs various types of guidance based on controllability and observability (C/O) measures and various heuristics fault' path and fault selection. Guided inconsistent path sensitization, a new method for low cost ATG, is discussed. A concurrent fault simulator is used to verify the generated test patterns. Experimental results show that ATWIG is very efficient in generating test patterns for combinational and low sequential circuits. Further improvements and heuristics are necessary for automatic test generation of highly sequential circuits. The relationship between C/O cost measures and A TWIG cost is discussed.

E. Trischler

Papers

Design for testability using incomplete scan path and testability analysis