Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.

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On circuit techniques to improve noise immunity of CMOS dynamic logic

A dynamic CMOS logic style, called multioutput domino logic (MODL), has been developed. In this logic style, single logic gates produce multiple functions, and a circuit's device count can be reduced by a factor of more than 2, depending on the degree of recurrence in the circuit. In addition, MODL circuits are, by construction, considerably more stable than other dynamic circuits including conventional domino. A 32-bit carry lookahead (CLA) structure which reduces the adder's worst-case path by two logic stages has also been devised. This CLA structure has been developed to effectively utilize the advantages of MODL. Taken together, these developments have resulted in two 32-bit CMOS adders, providing area and speed improvements of 1.5* and 1.7* over the combination of the domino and conventional CLA techniques. Both adders have been fabricated in a standard 0.9- mu m two-level metal CMOS technology, and measured results show that the straight adder has achieved 32-bit addition times of less than 3.1 ns at 25 degrees C with V/sub DD/+5.0 V. >

Ultrafast compact 32-bit CMOS adders in multiple-output domino logic

A high-speed 64-bit comparator using two-phase clocking dynamic CMOS logic with modified noninverting all-N-transistor block is presented. The pull-up charging and pull-down discharging of a comparator unit are accelerated by inserting two feedback MOS transistors between the evaluation N-block and the output. Detailed simulation results reveal appropriate L/W guidelines for the all-N-transistor block design. To increase throughput a parallel tree structure with two-phase clocks is employed. The comparator units of two adjacent layers are triggered by two out-of-phase clocks so that their individual outputs are pipelined without using extra hardware, e.g. latches. The operating clock frequency is 1.0 GHz while the compared output of two 64-bit binary numbers is done in 3.5 cycles.

1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking

In this paper, a novel all-N-logic single-phase high speed dynamic CMOS logic is introduced and analyzed. The circuits achieve high speed by eliminating the need for the low-speed P-logic blocks. The use of all-N-logic allows the speed of the proposed circuits to be two to three times the speed of conventional CMOS dynamic circuits. An 2:1 frequency divider, using proposed ANL2 circuits, is simulated using 0.8 /spl mu/m CMOS technology with the operating clock frequency reaching as high as 1.5 GHz. A pipelined 8-b carry generator of five-stacked NMOS transistors, which operates at a clock rate of over 710 MHz, has also been simulated. Experimental results show that the proposed circuits operate over 910 MHz implemented in a 1.2 /spl mu/m CMOS technology.

All-N-logic high-speed true-single-phase dynamic CMOS logic

An innovative dynamic logic family, clock-delayed (CD) domino, was developed to provide gates with either inverting or non-inverting outputs, and the high speed and layout compactness of dynamic logic. The characteristics of CD domino are demonstrated in two carry lookahead adder designs and three MCNC combinational logic benchmark circuits. The CD domino designs are compared to designs using static CMOS and standard domino logic. A circuit design tool was developed to automate the design of CD domino circuits. Simulations show a 32-bit CD domino adder comprised of four 8-bit full adders to be 30% faster than a 32-bit standard domino adder, anal a 32-bit CD domino adder comprised of a single 32-bit full adder to be 45% faster. In the combinational logic benchmark circuits, complex inverting and non-inverting gates were used to implement C1355, C3540, and b9. The CD domino circuits were 22%, 43% and 34% faster than their static CMOS counterparts of C1355, C3540 and b9, respectively.

Clock-delayed domino for adder and combinational logic design

A circuit structure called zipper CMOS is described. The major components in a zipper CMOS circuit are the zipper driver circuit and the alternative N- and P-dynamic logic blocks. The zipper driver generates four strobe signals that drive all the subsequent dynamic blocks. In this structure, the triggering threshold is controlled by the zipper driver and is less than conventional value of half the drain voltage. This allows zipper CMOS circuits to operate at least twice as fast as static CMOS circuits. The zipper driver also ensures stability of the circuit and prevents charge-sharing problems without any penalty in performance or silicon area utilization.

E. W. Szeto

Papers

Zipper CMOS