An improved clock generation circuit is provided that operates with a single input clock (20) frequency, and includes a Phase Locked Loop circuit (PLL) with a digital accumulator (65) in the feedback loop, in which either the Most Significant Bit or the Carry Bit of the binary adder is used as the modulated feedback clock to the phase/frequency detector (24) of the PLL. In one embodiment, a fixed add/phase amount is used to drive one of the inputs of the binary adder (60, 61) to generate a fixed output frequency. If it is desired to modulate the output frequency, then an Add Amount Modulator circuit (95) can be provided that presents a varying numeric value to one of the inputs of the binary adder. The MSB or Carry Bit is communicated to an address look-up table (84), which then outputs an address to a memory circuit, which in turn presents a different add amount to the binary adder. If a periodic modulation is desired, the address look-up table will point to add amounts that create a particular periodic output frequency profile, which could include a Spread Spectrum profile.

Method and apparatus for providing a clock generation circuit for digitally controlled frequency or spread spectrum clocking

A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The programmable array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the programmable blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.

Programmable microcontroller architecture(mixed analog/digital)

Highly accurate time interval measurement is achieved for an electrical waveform. The electrical waveform is sampled and converted to a series of voltages, and the series of voltages is interpolated in order to form a time tag list (222), using interpolations that are optimized for time interval measurement and analysis. The time tag list (222) accurately represents the times at which particular events of interest occur, and is used to generate displays and results analysis such as adjacent cycle jitter and accurate differential triggering and analysis.

Process and machine for signal waveform analysis

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Microcontroller Programmable System on a Chip

An interface, system and method enabling dynamic reconfiguration of an electronic device in a convenient and efficient manner. The interface enables basic operations, such as adding or deleting a device configuration and switching between different device configuration views/workspaces. In some embodiments, the system and method apply global device parameter values to each device configuration and/or allow only valid or legal states for device configurations beyond the first configuration. In another embodiment, the electronic device includes a microprocessor, a plurality of internal peripherals, an interconnecting component, an external coupling port, and a memory for storing instructions. The plurality of internal peripherals, the interconnecting component and the external coupling port are programmably configurable to perform a variety of functions. The memory stores a plurality of configuration images that define the configuration and configuration of the plurality of internal peripherals, the interconnecting component and the external coupling port. The instructions stored by the memory facilitate dynamic reconfiguration of the electronic device. Based upon the existence of a predetermined condition, the electronic device is automatically reconfigured by activating different configuration images.

Graphical user interface for dynamically reconfiguring a programmable device

An accumulator stores a signal representation of an accumulated angle that is incremented by an input angle in response to a reference clock pulse. The most significant bit (MSB) of the accumulated angle signals drives the input of a phase locked loop of the type that includes a loop filter, a frequency divider and a voltage controlled oscillator (VCO). A charge is injected into the loop filter during an overshoot interval during which the output of the frequency divider differs from the MSB. A compensating charge is injected into the loop filter to compensate for the charge injected during the overshoot interval. Jitter free spectrum spread clock pulses are provided by the VCO in response to the MSB.

Apparatus for reducing jitter of a spectrum spread clock signal and method therefor

A discriminator provides an output signal having an amplitude proportional to the frequency of a measured signal The output of the discriminator is connected to a differentiator circuit that provides an impulse signal proportional to a cycle to cycle frequency change of the measured signal

Earl William McCune

Papers

Apparatus for reducing jitter of a spectrum spread clock signal and method therefor

Apparatus for measuring cycle to cycle jitter of a digital signal and method therefor