Fuses and interconnects are fabricated by applying a metallic layer on a substrate and a fusible layer on the metallic layer. Portions of the fusible layer are removed to define discrete fuse elements having a necked portion. Portions of the metallic layer are removed to define interconnects. A portion of the metallic layer coextensive with the necked portion of the fuse elements is removed by selective side etching to form tapering portions separated by a gap without etching of the interconnects. The interconnects are protected from side etching by a separate mask layer or a mask layer used to form the interconnects may be heated to flow down over the sides of the interconnects.

Process for fabrication of fuse and interconnects

A technique is disclosed for trimming resistors and other passive circuit components buried in hybrid multilayer circuit structures. For example, resistors (13) are formed between two dielectric layers (11, 19) of a hybrid multilayer circuit structure (10). The multilayer circuit structure with the buried resistors is appropriately processed to provide a fired multilayer circuit structure. Trimming of the buried resistors is accomplished with a laser beam that cuts through dielectric material of the fired circuit structure to selectively remove part of the resistive material of the buried resistors. The values of the buried resistors may be tested with conductive elements (15, 17) that are conductively coupled to the buried resistors. The disclosed technique also contemplates the trimming of other buried passive circuit components such as capacitors, and further contemplates the use of other trimming methods such as abrasive, air jet, or water jet trimming.

Trimming passive components buried in multilayer structures

A thin film foil resistor is disclosed wherein a thin metallic foil is bonded to an insulating substrate and a circuit path is formed on the foil by photographic artwork-etching techniques. After the circuit is formed, the structure is subjected to another etching process to reduce the thickness of the foil circuit thereby adjusting the value of the resistor. Terminal lands of the circuit are electroplated and the connecting leads are soldered to the lands. The value of the resistor is finally adjusted by use of a laser beam, and the resistor is encapsulated.

Metal foil resistor

A SiCr microfuse, deletable either by electrical voltage pulses or by laser pulses, for rerouting the various components in an integrated circuit, as where redundancy in array structures is implemented, and the method of fabricating same, at any wiring level of the chip, by utilizing a direct resist masking of the SiCr fuse layer to eliminate problems of mask damage and residual metal adjacent the fuse.

Structure and fabrication of SiCr microfuses

Thin-film microcircuit structures passivated with silicon nitride are provided in which included electrical components containing nickel, chromium or other nitride-forming metals are encapsulated in an oxide material, preferably silicon oxide. The metal-containing components are thus prevented from reacting with the silicon nitride passivation coating during through-passivation laser trimming of the components.

Passivated thin-film hybrid circuits

An arrangement of thin film resistive layers for hybrid microcircuits thatliminates electrical contact problems and provides a means for obtaining high precision by trimming. A thin resistive film is deposited on an insulating substrate over a mask. Without breaking vacuum, a second resistive film which is not subject to oxidation is deposited over the first resistive film. The second resistive film is then etched away from portions which are not used as contact points. Since the second resistive material has a different resistivity, it is also used for low value resistive portions in multiple resistor networks.

Chromium-silicon oxide thin film resistors

A binary decision apparatus comprising a control unit which generates the nary decision apparatus' control signals from an operation code contained in the first byte of an instruction, a program counter which provides addressing for an external program memory, and a memory buffer register for holding digital instruction data provided by the external program memory. External control signals provided to the binary decision apparatus include a single phase system clock, a system reset signal and a wait signal that can be used to single-step the binary decision apparatus. Program instructions are provided from the external program memory to the binary decision apparatus via an eight-bit data bus, while an internal twelve-bit data bus routes digital information between the registers and counters of the binary decision apparatus. The binary decision apparatus of the present invention also includes an input register for receiving and then latching into the register external binary signals, an output register which is a bit or word address register that provides the digital logic output signals for the binary decision apparatus, a flag register in which status bits are stored and counters and registers for performing the counting and other functions/operations of the binary decision apparatus.

Eddie B. Croson

Papers

Chromium-silicon oxide thin film resistors

Process control apparatus for executing program instructions