A method and circuit adaptively adjust the timing offset of a digital signal relative to a clock signal output coincident with that digital signal to enable a latch receiving the digital signal to store the digital signal responsive to the clock signal. The digital signal is applied to the latch, and stored in the latch responsive to the clock signal. The digital signal stored in the latch is evaluated to determine if the stored digital signal has an expected value. The timing offset of the digital signal is thereafter adjusted relative to the clock signal. and the digital signal is once again stored in the latch responsive to the clock signal at the new timing offset. A number of digital signals at respective timing offsets relative to the clock signal are stored and evaluated, and a final timing offset of the digital signal is selected from the ones of the timing offsets that cause the latch to store the digital signal having the expected value. The timing offset of the digital signal is thereafter adjusted to the selected final timing offset. A read synchronization circuit may adaptively adjust the timing offset of digital signals in this manner, and such a read synchronization circuit may be utilized in many types of integrated circuits, including packetized dynamic random access memories, memory systems including a memory controller and one or more such packetized dynamic random access memories, and in computer systems including a plurality of such packetized dynamic random access memories.

Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same

A integrated circuit, such as a memory integrated circuit, includes a vernier clock adjustment circuit receiving an input clock signal and providing a rising-edge clock signal representing the input clock signal delayed by a rising-edge delay and providing a falling-edge clock signal representing the input clock signal delayed by a falling-edge delay. An edge triggered circuit receives data and the rising-edge and falling-edge clock signals, and stores data at the rising-edge of the rising-edge clock signal and at the falling-edge of the falling-edge clock signal. One form of the invention is a memory system having a memory controller coupled to memory modules through data and command busses. Each memory module includes the vernier clock adjustment circuitry.

Clock vernier adjustment

A system for adjusting the phase of an internal clock signal relative to an external clock signal in a packetized dynamic random access memory device. The system applies a plurality of initialization packets to the memory device that are captured in a shift register responsive to a transition of the internal clock signal. However, the phase of the internal clock signal is sequentially incremented after each initialization packet has been captured in the shift register. After a plurality of initialization packets have been captured, an evalution circuit identifies which phases of the internal clock signal clocked the shift register at the proper time to accurately capture each initialization packet. A single phase of the internal clock signal is then selected from within the range of internal clock signal phases that successfully captured initialization packets. This selected phase of the internal clock signal is used during normal operation of the memory device.

Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same

A synchronous clock generator is comprised of a delay-locked loop for producing a plurality of signals in response to an external clock signal. Each of the plurality of signals is delayed a predetermined period of time with respect to the external clock signal. A plurality of multiplexers is responsive to the plurality of signals for producing at least one clock signal in response to control signals input to the plurality of multiplexers. A clock driver is provided for driving the clock signal. A variable delay circuit is positioned to delay the external clock signal before input to the delay-locked loop. A compound feedback loop is responsive to certain of the plurality of signals for producing a control signal input to the variable delay circuit.

Synchronous clock generator including a compound delay-locked loop

A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.

Delay-locked loop with binary-coupled capacitor

A delay element for fine tuning the position in time of timing edges of an input signal, comprising a first and a second inventer, each comprising a data input, a control input and a data output. The delay element further comprises a node comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage is included for applying a biasing voltage to the first and second control inputs to thereby control the amount of charge supplied to the node. Finally, the variable capacitance means is connected to the node for applying finite amounts of capacitance to the node to delay and thereby fine tune in time the timing edges of the input signal propagating from the first inverter to the second inverter.

Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations

An NMOS analog voltage comparator is disclosed having two matching cascaded inverter-pairs. The comparator has fast response time, is not sensitive to temperature variations while operating, and operates independent of integrated circuit parameter variations encountered during circuit manufacture.

NMOS analog voltage comparator

A pseudo-NMOS or PMOS inverter comprises a first p-type or n-type field effect transistor (FET) (502, 504), and a second n-type or p-type FET (506, 508) having second gate, source, and drain electrodes. The second gate electrode forms an input to the inverter, and the second drain electrode is connected to the first drain electrode to thereby form an output node of the inverter. A voltage supply is connected to the first source and the second source electrodes. An adjustable control voltage (112) is applied to the first gate electrode to thereby determine the conductivity of the first FET. The amount of current flowing from the voltage supply to the output node is regulated by changing the adjustable control voltage.

Pseudo-NMOS or PMOS inverter

A delay element (210) for fine tuning the position in time of timing edges of an input signal (203), comprising a first and a second inventer (307, 314), each comprising a data input, a control input and a data output. The delay element (210) further comprises a node (310) comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage (112) is included for applying a biasing voltage to the first and second control inputs to thereby control the amount of charge supplied to the node (310). Finally, the variable capacitance means (308) is connected to the node (310) for applying finite amounts of capacitance to the node to delay and thereby fine tune in time the timing edges of the input signal (203) propagating from the first inverter (307) to the second inverter (314).

Edward Gary Pumphrey

Papers

Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations

NMOS analog voltage comparator

Pseudo-NMOS or PMOS inverter

Pseudo-NMOS programmable capacitance delay element