Fast, efficient logic simulators are an essential tool in modern VLSI system design. Logic simulation is used extensively for design verification prior to fabrication, and as VLSI systems grow in size, the execution time required by simulation is becoming more and more significant. Faster logic simulators will have an appreciable economic impact, speeding time to market while ensuring more thorough system design testing. One approach to this problem is to utilize parallel processing, taking advantage of the concurrency available in the VLSI system to accelerate the logic simulation task.Parallel logic simulation has received a great deal of attention over the past several years, but this work has not yet resulted in effective, high-performance simulators being available to VLSI designers. A number of techniques have been developed to investigate performance issues: formal models, performance modeling, empirical studies, and prototype implementations. Analyzing reported results of these techniques, we conclude that five major factors affect performance: synchronization algorithm, circuit structure, timing granularity, target architecture, and partitioning. After reviewing techniques for parallel simulation, we consider each of these factors using results reported in the literature. Finally we synthesize the results and present directions for future research in the field.

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Parallel logic simulation of VLSI systems

Design verification via simulation is an important component in the development of digital systems. However, with continuing increases in the capabilities of VLSI systems, the simulation task has become a significant bottleneck in the design process. As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation. This tutorial describes the current state-of-the-art in parallel logic simulation, including parallel simulation techniques, factors that impact simulation performance, performance results to date, and the directions currently being pursued by the research community.

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Parallel Logic Simulation of VLSI Systems

A study is made of the global routing of multiterminal nets. The authors propose a novel global router. Each step consists of finding a tree, called Steiner min-max tree, that is, a Steiner tree with the maximum-weight edge minimized (real vertices represent channels containing terminals of a net, Steiner vertices represent intermediate channels, and weights correspond to densities). An efficient algorithm is presented for obtaining a Steiner min-max tree, in a weighted graph. Experimental results on difficult examples, randomly generated data, master slice chips, and benchmark examples from the physical design workshop are very promising. (In all cases, previous results have been improved.). >

A powerful global router: based on Steiner min-max trees

This paper presents a methodology for empirically determining the amount of parallelism on a CMOS VLSI chip. Six chips are measured, and the effect of input choice and circuit size is studied. The unexpectedly low parallelism measured here suggests that certain strategies for parallel simulators may be doomed, and earlier efforts to extrapolate parallelism from small circuits to large circuits may have been overly optimistic.

An empirical study of on-chip parallelism

One of the significant difficulties in partitioning logic circuits for distributed simulation is the lack of a priori knowledge concerning the evaluation frequency of individual circuit elements. A number of researchers have resorted to pre-simulation to estimate these evaluation frequencies. In this paper we empirically investigate the wisdom of relying on pre-simulation results, and evaluate the degree to which early evaluation frequencies predict later evaluation frequencies. The results show that, for simulations that use random input vectors, pre-simulation has clear merit in predicting circuit element evaluation frequency. This supports the use of pre-simulation as an input to circuit partitioning algorithms.

Evaluating the use of pre-simulation in VLSI circuit partitioning

In this dissertation I describe the algorithms, architecture, and performance of a computer called the FAST-1--a special-purpose machine for switch-level simulation of VLSI circuits. The FAST-1 does not implement a previously existing simulation algorithm. Rather its simulation algorithm and its architecture were developed together. The FAST-1 is data-driven, which means that the flow of data determines which instructions to execute next. Data-driven execution has several important attributes: it implements event-driven simulation in a natural way, and it makes parallelism easier to exploit.
Although the architecture described in this dissertation has yet to be implemented in hardware, it has itself been simulated using a 'software implementation' that allows performance to be measured in terms of read-modify-write memory cycles. The software-implemented FAST-1 runs at speeds comparable to other software-implemented switch-level simulators. Thus it was possible to collect an extensive set of experimental performance results of the FAST-1 simulating actual circuits, including some with over twenty thousand transistors. These measurements indicate that a hardware-implemented, uniprocessor FAST-1 offers several orders of magnitude speedup over software-implemented simulators running on conventional computers built using similar technology.
Additional speedup over a uniprocessor can be obtained using a FAST-1 multiprocessor, that is constructed using multiple FAST-1 uniprocessors that are interconnected by one or more broadcast busses. In order for a FAST-1 multiprocessor to exploit the parallelism available in simulations, the FAST-1 representation of circuits must be carefully partitioned onto the processors. Although, even simple versions of the partitioning problem are NP-complete, I show that an additional order of magnitude speedup can be obtained by using a multiprocessor FAST-1 and fast heuristic partitioning algorithms.

Edward Harrison Frank

Papers

A data-driven multiprocessor for switch-level simulation of vlsi circuits