A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).

Method of fabricating a raised source/drain transistor

An aluminum electrolytic capacitor having an excellent short-circuit resistance, high capacitance, long life, and low equivalent series resistance (ESR) is provided. For this purpose, the aluminum electrolytic capacitor includes a capacitor element having a positive electrode foil, a first separator, a negative electrode foil, and a second separator, which are sequentially laminated one on another and wound together. After the capacitor element is impregnated with a driving electrolyte solution and housed in a metallic case, an open end of the metallic case is sealed with a sealing material. A ratio of B/A, i.e. a ratio of total thickness B of the first and second separators after winding with respect to total thickness A of the first and second separators before winding, is set in the range from 0.5 to 0.8.

Aluminum electrolytic capacitor

A method of forming a bipolar transistor comprising the steps of forming a base region in a semiconductor structure and disposing an emitter region on a surface of a first portion of the base region, the emitter region having upper and side surfaces. An active base region is formed in the first portion of the base region and an inactive base region is formed in a second portion of the base region adjacent to the first portion and the side surface of the emitter region. A layer of insulating material is formed over a surface of the inactive base region and over the upper and side surfaces of the emitter region. Portions of such layer are selectively removed to expose the upper surface of the emitter region and a portion of the surface of the inactive base region, and to maintain a region of insulating material between the exposed surface portion of the inactive base region and the side surface of the emitter region. Silicide contacts are formed on the exposed surface portion of the inactive base region and the exposed upper surface of the emitter region, with the insulating material region insulating such contacts from each other. With such arrangement, the spacing between the base and emitter contacts may be substantially reduced, such as to the width of the insulating material region, thereby reducing the size (i.e. width), base-to-emitter resistance, base contact resistance and base-to-emitter and base-to-collector capacitance of the bipolar transistor.

Method of forming a bipolar transistor having closely spaced device regions

A method for manufacturing a non-volatile memory comprising the steps of: (i) forming a first electrode on a semiconductor substrate having a first insulating film; (ii) implanting impurity ions to an area adjacent to one side of the first electrode while masking at least an area adjacent to another side of the first electrode; (iii) forming a second insulating film on the semiconductor substrate including the first electrode, followed by depositing a conductive film on the entire surface of the second insulating film; (iv) implanting impurity ions into the semiconductor substrate via the conductive film; and (v) patterning the conductive film to constitute a second electrode.

Method for manufacturing an asymetric non-volatile memory

In a method of resin-sealing a semiconductor device having a circuit board with an IC thereon, a metal mold formed of upper and lower metal molds is prepared. The upper metal mold has a pressing member, and the lower metal mold has a cavity for mounting the circuit board therein, a pinpoint gate formed at a lower portion of the cavity and a runner section formed below the cavity and communicating with the pinpoint gate. The circuit board is positioned in the cavity of the lower metal mold, and is set such that the IC faces downward. A rear surface of the circuit board where the IC is not mounted is pressed by the pressing member, and a resin is filled in the cavity through the runner section and the pinpoint gate to thereby seal the IC mounted on the circuit board by the resin.

Method of resin-sealing semiconductor device

PURPOSE:To enable arbitrary selection of the forward voltage of a Schottky barrier diode within a certain range by a method wherein a metal silicide film formed on an Si substrate is etched into a required film thickness by sputter etching. CONSTITUTION:On etching treatment of the Si substrate 7 where a Pt silicide film 4 has been formed, the film and an oxide film 2 are both removed in surface layers. The speed of etching removal of the film 2 is smaller than that of the film 4. Therefore, the effect of sputter etching can be thought only as the reduction in the thickness of the film 4. Since the amount of this removal increases in proportion to time if the high frequency power is kept constant, the thickness of the film 4 can be controlled with the sputter etching time. An electrode metal 6 and a barrier metal 5 inhibiting the reaction of the film 4 with the metal 6 are formed on the substrate, and then the Schottky barrier diode having an arbitrary forward voltage is formed.

Eguchi Youichi

Papers

Manufacture of semiconductor device