Immense growth in technology and ever-increasing computational complexities in image and signal processing algorithms requires robust and efficient hardware software co-design methodologies. Multiplication operation forms the core of such extensively used techniques like correlation, convolution filtering etc. and it is one of the major contributing factors for deteriorating the system performance in terms of latency and throughput. This paper presents a design and implementation framework of enhanced multiplier based on prehistoric “Indian Vedic mathematics sutras”. Presented architecture is based on Vedic multiplication. The computation of partial multiplication is performed in parallel manner and further added to generate the result. In this work, a module of single carry save adder for performance enhancement replaces multiple adders. The partial multiplication terms are accustomed by concatenation. The Proposed design is simulated and implemented using Xilinx ISE Design Suit 14.5. Comparative analysis demonstrates that our proposed architecture for multiplication produce better results even for higher bits in terms of speed.

Design and simulation of enhanced 64-bit Vedic multiplier

Ancient mathematics is the oldest Indian system of mathematics; it has distinct technologies of solution based on formulae or sutras. Vedic mathematics sutra is very useful for numerous mathematical operations. There are 16 sutras in Vedic mathematics out of which Urdhva Tiryagbhyam sutra has been proved to be efficient in implementing multiplication. In any high end processor, multiplication plays a very vital role as the processor's performance depends on the multiplication. Many architectures are proposed for implementing multiplier but multiplier based on Vedic mathematics results in high speed computation.

Power Efficient and High Speed Multiplier Bbased on Ancient Mathematics: A Review

Various “arithmetic operations”, “signal and image processing systems” and “communication devices” incorporate multipliers as the basic element. Vedic mathematics is an ancient mathematical system which focuses on solving tedious problems using 16 Vedic Sutras in a simpler and faster manner. The evolution of technology demands for “low power design” in the domain of integrated circuit. This led to the invention of varied adiabatic logic for low power operations. The uniqueness of Vedic mathematics and adiabatic logic is combined to design high speed and power-efficient multipliers. In this paper, a new adiabatic logic “Complementary Pass Transistor Adiabatic Logic” (CPAL) is used to design 8-bit Vedic multiplier. To authenticate the superiority of the proposed design, comparative performance analysis is carried out with respect to CMOS and other adiabatic logics like 2N-2N2P and “Efficient Charge Recovery Logic” (ECRL) based on 150nm technology. The simulation has been accomplished by the use of TANNER SPICE 16 tool. Simulation result validates the reduction of Power Delay Product (PDP) of the proposed CPAL Vedic multiplier design in comparison to the aforementioned techniques. The proposed technology offers a power-efficient solution for modern designs.

Design of Power Efficient Vedic Multiplier using Adiabatic Logic

Modern computational devices are in need of efficient and optimized hardware architectures with low power and reduced computational complexity. This work presents an efficient and optimized dedicated cube architecture using the proposed modified Yavadunam Sutra Algorithm of Vedic Mathematics. Hardware implementation results of the proposed Vedic cube architecture for input bit-lengths (4-, 8-, 16- and 32-bit) are presented using Field Programmable Gate Array (FPGA) platform. The proposed cubic architecture on modified Yavadunam Sutra outperforms existing state-of-the-art dedicated cube units in terms of combinational delay and area (No. of four-input/slice LUTs) on a FPGA platform. Comparison results of the proposed dedicated cube architecture with reported Vedic cube architectures are also presented.

Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA

In integrated circuits (ICs) system, computational performance is limited by its performance, and since the execution time is dominated by the multiplication factor because of that high speed multiplier is much more important in DSP applications. This paper presents an efficient multiplier design using FinFET technology using gate diffusion input (GDI). The quantum-based threshold voltage has been significant when the FinFET is scaled to sub 18 nm; these effects are modeled by solving the transistor channel with the change of material parameters. Adder is a fundamental block in numerous digital circuits, fluctuations degrading the device performance with the aim that altering FinFET design parameters to get rid of variations. The proposed FinFET Vedic GDI adder is analyzed using physics-based hot carrier effect/compact model for prediction of FinFET performance degradation due to the interface state, to reduce cost and time-time market in advanced process development. This design uses less number of transistors than the conventional CMOS-based multiplier designs. By employing the FinFET-GDI technique, there is an extensive decrease in power and delay of the circuit. Design also solves the threshold drops problem of original GDI cell resulting in better output signals. The proposed methodology is implemented in tanner tools using TSMC library. Design technology co-optimization (DTCO) obtains high speed, low power and reliability of practical MOSFETS. The simulation results show the desired accuracy, speed, power and reliability of proposed adder structure by lowering the fluctuations of digital circuits. 

Analytical Variable Execution of GDI Vedic Multiplier Using FinFET Full Adder

This paper presents design of optimized high speed and low power Vedic multiplier based on Vedic sutra Urdhva Tiryagbhyam. Adiabatic logic is used to reduce the power consumption of Vedic multiplier and its performance is evaluated by comparing it with conventional MOS design. The power consumption of Adiabatic Vedic multiplier is less than power consumed by Vedic multiplier without adiabatic logic is analyzed. The circuit 2×2, 4×4 Vedic multipliers are designed and simulated on 180nm technology using Tanner EDA Tool 13.0.

Ekta Masurkar

Papers

Implementation of optimized vedic multiplier using CMOS technology