A hardened network-on-chip design using runtime hardware Trojan mitigation methods

Network-on-Chip (NoC) architectures employing packet-based communication are being increasingly adopted in System-on-Chip (SoC) designs. In addition to providing high performance, the fault tolerance and reliability of these networks is becoming a critical issue due to several artifacts of deep sub-micron technologies. Consequently, it is important for a designer to have access to fast methods for evaluating the performance, reliability, and energy-efficiency of an on-chip network. Towards this end, first, we propose a novel path-sensitive router architecture for low-latency applications. Next, we present a queuing-theory-based model for evaluating the performance and energy behavior of on-chip networks. Then the model is used to demonstrate the effectiveness of our proposed router. The performance (average latency) and energy consumption results from the analytical model are validated with those obtained from a cycle-accurate simulator. Finally, we explore error detection and correction mechanisms that provide different energy-reliability- performance tradeoffs and extend our model to evaluate the on-chip network in the presence of these error protection schemes. Our reliability exploration culminates with the introduction of an array of transient fault protection techniques, both architectural and algorithmic, to tackle reliability issues within the router's individual hardware components. We propose a complete solution safeguarding against both the traditional link faults and internal router upsets, without incurring any significant latency, area and power overhead.

Design and analysis of an NoC architecture from performance, reliability and energy perspective

Reconfigurable systems have evolved as a more comprehensive and better known area in the last years. Reconfigurability is strictly related to the ability to change: the more flexible a system is, the greater is its reconfigurability. Reconfiguration can provide the systems characteristics as self-adaptation, allowing their resources to be used according to the environment in which they are found and, consequently, extracting a better use of these resources. Unmanned Aerial Vehicles (UAVs), mine hoists, mobile robots, and balloon systems are some applications where self-adaptation and reconfiguration are important. Some reconfigurable systems are able to plan their reconfiguration at runtime, i.e., the system sets its new configuration while running. These systems are called Dynamically Reconfigurable Systems (DRSs). This paper aims to investigate DRSs seeking to answer four specific questions: (i) how the different kinds of DRSs are classified in the literature and what is their definitions; (ii) what are the hardware and software platforms, methodologies and techniques engaged in DRSs; (iii) what are the domains of application of DRSs; and, (iv) which countries lead the number of publications in DRSs. To do that, a systematic literature review was conducted, where, at the end, 85 articles between 1995 and 2017 were completely read.

Dynamically Reconfigurable Systems: A Systematic Literature Review

This paper evaluates the Triplet Based Architecture, TriBA — a new idea in chip multiprocessor architectures and a class of Direct Interconnection Network (DIN). TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors so that advantageous features of group locality can be fully and efficiently utilized. Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. We propose a new criterion in performance evaluation that is based on the concept of locality in an interconnection network, the “lower layer complete connect”. Our proposed criterion depicts how completely a processing node is connected to all its neighbors. TriBA is compared with 2D Mesh and Binary Tree as static interconnection network. The comparison / evaluation is enumerated from three orthogonal view points, viz., computational speed, physical layout and cost. Our analysis concludes that TriBA is computationally efficient interconnection strategy that exploits group locality in processing nodes.

Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip (MP-SoC)

Reconfigurable on-chip interconnection networks for high performance embedded SoC design

System level design for many-core chips includes general system architecture design, MPSoC design as a set of nodes and their interconnection. It requires adequate models and methodology to estimate MPSoC interconnection characteristics in complexity and power consumption to make decisions at the system level design stage of an MPSoC project. To determine performance and power consumption of MPSoC we suggest the simplified model of tentative wires for evaluating interconnection topology at early stages of design process, to correspond them with technology characteristics, with power dissipation and power consumption. With this approach we reason about many-core SoC interconnections, place and route, methodology for system level design of MPSoC interconnections.

Complexity and low power issues for on-chip interconnections in MPSoC system level design

Nowadays in the aerospace industry the router-based onboard embedded networks gradually replacing bus-based networks because they are already not satisfy the aerospace performance requirements. The SpaceWire, GigaSpaceWire and SpaceFibre standards are developing to meet the increasing aerospace requirements. The important requirement for any aerospace embedded onboard network is a transmission of control information and system signals in hard real time. These signals can be synchronous and asynchronous, periodic and aperiodic, with or without acknowledges. The distributed interrupt mechanism is used for asynchronous signal transmission and it is included into the second edition of SpaceWire standard. The Time-code propagation mechanism is used for synchronous signal transmission in SpaceWire. The broadcast messages mechanism is used for transmission of different system signal in SpaceFibre but it does not quite meet the requirements of hard real time. In this paper the authors consider the asynchronous signals transmission with and without acknowledges. The aims of this paper are following: 1 theoretically investigate the distributed interrupt mechanism; 2 to prove its properties; 3 to specify parameters and limitations; 4 to derive the time characteristics. For these purpose the authors developed the analytical model which describe the distributed interrupt propagation mechanism in terms of the graph theory.

Asynchronous Hard Real Time Signals Transmission in Embedded Networks

In this article we consider the deadlock-free routing problem for onboard SpaceWire network with redundant devices We work with static routing, it means that, routing tables are calculated and uploaded into the switches before launch the SpaceWire network We solve deadlock-free problem with Up/Down routing approach, which is based on acyclic directed network graph To build acyclic directed graph we modify the original algorithm of DFS based creating spanning tree To find the routes of data transmission in the network we convert created directed graph to channel dependency graph Also in this article we provide an example and explanation of our algorithms for deadlock-free routing in SpaceWire network

Deadlock-Free Routing in SpaceWire Onboard Network

An ability of faults mitigation becomes one of the main requirements for network-on-chip (NoC) embedded systems that are manufactured with thin design rules. Other requirements are for area, power consumption and QoS. Altogether these requirements lead to inconsistencies in NoC development process. In this paper we discuss approaches for resolving this conflict by the use of the dynamically reconfigurable NoC. We suggest a methodology for development of NoC with fault mitigation support The methodology allows to take into account specifics of design process and operating conditions in the implementation of a particular project. For verification of the suggested approach we use analysis and simulation. We suggest an approach to simulation that enables dynamic failure injection.

Reconfigurable NoC development with fault mitigation

SpaceFibre based spacecraft network is used as a case study of the real network, which SpaceWire based implementation was analyzed in [1]. The network structure has tree-based structure, includes dozens of different data sources (such as Telemetric System, Radiation Monitoring System, Control Block of Onboard Complex) and some data processing nodes (such as Central Computing Machine, Computer of the Engine Bay, Cosmonaut Consoles).

Elena Suvorova

Papers

Complexity and low power issues for on-chip interconnections in MPSoC system level design

Asynchronous Hard Real Time Signals Transmission in Embedded Networks

Deadlock-Free Routing in SpaceWire Onboard Network

Reconfigurable NoC development with fault mitigation

SpaceFibre based spacecraft network case study