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Enric Herrero Abellanas
Researcher at Intel
Publications - 12
Citations - 165
Enric Herrero Abellanas is an academic researcher from Intel. The author has contributed to research in topics: Cache pollution & Cache. The author has an hindex of 5, co-authored 12 publications receiving 165 citations.
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Patent
Method and apparatus for distributed and cooperative computation in artificial neural networks
Frederico Pratas,Ayose Falcón,Marc Lupon,Fernando Latorre,Pedro Lopez,Enric Herrero Abellanas,Georgios Tournavitis +6 more
TL;DR: In this paper, an apparatus and method for distributed and cooperative computation in artificial neural networks is described, which comprises an input/output (I/O) interface, a plurality of processing units communicatively coupled to the I/O interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each unit processing at least a portion of the data for the inputs and weights to generate partial results.
Patent
Reconfigurable processing unit
Marc Lupon,Enric Herrero Abellanas,Ayose Falcón,Fernando Latorre,Pedro López,Frederico Pratas +5 more
TL;DR: In this paper, a processor core and a number of calculation modules that each is configurable to perform any one of operations for a convolutional neuron network system are configured to perform convolution operations, averaging operations and dot product operations.
Patent
Processing device for performing convolution operations
Enric Herrero Abellanas,Marc Lupon,Ayose Falcón,Frederico Pratas,Fernando Latorre,Pedro Lopez +5 more
TL;DR: In this paper, a convolutional filter is applied to a plurality of input data elements represented by a two-dimensional array, with the convolver unit comprising a multipliers coupled to two or more sets of latches.
Patent
Selective provision of error correction for memory
Javier Carretero Casado,Xavier Vera,Daniel Sanchez,Tanausu Ramirez,Enric Herrero Abellanas,Nicholas Axelos +5 more
TL;DR: In this paper, a memory controller may be configured to selectively employ the second error correction arrangement to complement the first correction arrangement, which enables correction of at least one bit error more than the first level.
Patent
Vulnerability estimation for cache memory
Javier Carretero Casado,Xavier Vera,Tanausu Ramirez,Daniel Sanchez,Enric Herrero Abellanas,Nicholas Axelos +5 more
TL;DR: In this article, the first counter is reset when a write or other cache access that modifies data in the cache element occurs, and the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable.