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Eric Schnarr

Researcher at University of Wisconsin-Madison

Publications -  7
Citations -  747

Eric Schnarr is an academic researcher from University of Wisconsin-Madison. The author has contributed to research in topics: Executable & Shared memory. The author has an hindex of 6, co-authored 7 publications receiving 743 citations.

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Proceedings ArticleDOI

EEL: machine-independent executable editing

TL;DR: EEL supports a machine- and system-independent editing model that enables tool builders to modify an executable without being aware of the details of the underlying architecture or operating system or being concerned with the consequences of deleting instructions or adding foreign code.
Journal ArticleDOI

Fast out-of-order processor simulation using memoization

TL;DR: This new out-of-order processor simulatol; FastSim, uses a variation on memoization to cache microarchitecture states and the resulting simulator actions, and then "fast forwards" the simulation the next time a cached state is reached.
Proceedings ArticleDOI

Facile: a language and compiler for high-performance processor simulators

TL;DR: Facile, a domain-specific language for writing detailed, accurate micro-architecture simulators, is described, which can be compiled, using partial evaluation techniques, into fast-forwarding simulators that achieve significant performance improvements with far less programmer effort.

Implementing Fine-grain Distributed Shared Memory on Commodity SMP Workstations

TL;DR: This paper presents a meta-modelling system that automates the very labor-intensive and therefore time-heavy and expensive and expensive process of manually cataloging and cataloging the input and output of a distributed system.
Proceedings ArticleDOI

Instruction scheduling and executable editing

TL;DR: Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit, which opens the exciting possibility of low-cost instrumentation for measurement, simulation, or emulation on superscalar SPARC processors.