A hardware-software system design optimization tool is described. The tool allows a designer to optimize the system performance by allowing him to select software components of the system and move them to a hardware representation. The software components are selected by using a performance profile of the system, which comprises time data related to execution of the software components, memory and bus transactions. In another aspect, the tool automatically collects the performance data and generates the performance profile. In another aspect, performance data is collected by modeling the execution of the hardware-software system. In another aspect, hardware-software system is modeled again after selected software components are moved to a hardware representation to inquire whether the move improved overall system performance.

Automated repartitioning of hardware and software components in an embedded system

A tool is described herein for optimizing the design of a hardware-software system. The tool allows a designer to evaluate the potential improvement in system performance that may be realized by moving selected software components of the system to a hardware implementation. In one aspect, the tool automatically generates a performance profile of an original form of the system. The performance profile of the original form of the system may be used to select software components of the system to be moved to hardware. In another aspect, the tool generates an estimated performance profile of a repartitioned form of the system by modifying the performance profile of the system. The estimated performance profile of the repartitioned system is compared to the performance profile of the original form of the system to verify benefits, if any, of repartitioning. Such verification is accomplished without the need to actually repartitioning the system or measuring the performance of the entire repartitioned system.

Repartitioning performance estimation in a hardware-software system

We present a co-synthesis algorithm that combines repartitioning and HW /SW partitioning of the processes in a system specification to provide an efficient design space exploration stractegy. The algorithm is defined on a Partial Order based Model (POM), which is an alternative to model concurrency at a high level of abstraction and has a concise symbolic representation, mainly for systems with high degree of parallelism, as well as allows the use of efficient reachability analysis techniques based on partial order reductions. Our repartitioning algorithm generates a partitioning tree, where the possible partitions of the processes in a specification are represented in a systematic way, according to the communication among them. The HW /SW partitioning algorithm is applied on these possible partitionings and will select the one that minimizes the communication cost between the partitions. In this paper, we will just present the repartitioning: HW /SW partitioning and performance/cost estimates algorithms and how they are used in our design space exploration stractegy. The reported experimental results show the efficiency: when compared with related works: and practicability of our co-synthesis algorithms.

A Repartitioning and HW/SW Partitioning Algorithm to the Automatic Design Space Exploration in the Co-Synthesis of Embedded Systems

In this paper we present a co-synthesis approach based on the state space reachability analysis of the system specification, which is captured using a partial order based model for concurrency The partial order based model (POM) combines the concept of relations between events from event structures for the modeling of intercommunicating concurrent behaviors and the Chu space semantics for these relations in terms of logical formulas The POM is used in our approach as an intermediate representation, which permits a concise symbolic representation, mainly for systems with high degree of parallelism, and an efficient BDD based implementation of analysis and synthesis algorithms We introduce the partial order based model for concurrency and show how to use it in modeling at the system level We present a symbolic representation for the model and its implementation using BDDs and we give reachability analysis algorithms that are applied to the estimation of performance and costs during the co-synthesis and to the formal verification of properties Finally we describe our co-synthesis approach based on the formal model

F.A.M. do Nascimento

Papers

A Repartitioning and HW/SW Partitioning Algorithm to the Automatic Design Space Exploration in the Co-Synthesis of Embedded Systems

A co-synthesis approach based on symbolic reachability analysis