A method for providing test vectors adapted to test very large scale integrated circuit devices includes the steps of measuring testability employing a test counting procedure to provide a plurality of test count matrices. Sensitivity values are then enumerated by driving individual sensitivity values forwardly and rearwardly through the circuit, starting at the input terminals, until the test counts are accumulated. The enumerations define test vectors capable of testing the actual circuit. If the circuit includes reconvergent fanout loops, then these loops are enumerated first to provide partial solutions adopted during subsequent global enumeration.

Method for test generation

This paper takes a critical look at the role testability analysis has been playing in IC design and provides an insight into what role it should assume in the future. Traditionally, testability analysis was used to derive information on how testable a circuit is early enough in the design cycle so that the design could be modified to improve its testability before running either the fault simulation or the actual testgeneration programs. This approach would avoid wasting precious computer resources in using those two programs. More recently, two rather important applications have also been identified. The first is to use testability-analysis results as heuristics to guide the test-generation process in search of a solution (test vector). Testability-analysis programs have also been used to derive information normally provided by fault simulation. Due to these developments and the potential usefulness of the information it can provide, testability analysis is gaining more importance in the design cycle of integrated circuits.

Based upon our recent experiences in developing testability analysis and test-generation programs, we believe that testability analysis will eventually replace fault simulations. However, it is imperative that the burden not be shifted to the test-generation or testing processes. Instead, the ultimate role of testability analysis is to provide vital information for generating tests directly. It would provide at least an approximate solution to a very complex (NP-complete) problem through algorithms of less complexity. This approach promises a final solution to the challenge of VLSI test generation.

F. C. Wang

Papers

Testability analysis: what role should it play in IC design?