A CODEC, fabricated in 3.3-V CMOS, provides the low-voltage transmitter and receiver interfaces between the modem digital signal processing engine and the high-voltage hybrid circuitry for either the central office or the remote terminal ends of the subscriber loop, configurable by metal mask option. Extensive use of digital interpolation filters in the transmitter, decimation filters in the receiver, and oversampled data converters minimize the complexity of analog filters. On-chip filtering and 14-bit data converters support echo-canceling modems without requiring external filters. With additional external filters, frequency-division duplexing is also supported. The die area is 67.5 mm/sup 2/. The power dissipation in the central office and remote terminal are 600 and 760 mW, respectively.

Codec for echo-canceling, full-rate ADSL modems

An oversampled digital-to-analog converter for use in ADSL central office modems has been integrated in 0.18-/spl mu/m CMOS technology. The converter features a multi-bit semi-digital filter for reconstruction and a digital pre-emphasis filter that boosts the SNR of subcarriers affected by noise shaping and flattens the overall in-band magnitude response. A resampled impulse response is employed to simplify the implementation of the semi-digital filter. The combination of digital and semi-digital filtering allows the design to meet all ADSL performance requirements with only 180 current cells and a third-order analog low-pass reconstruction filter. When sampling at 200 MSample/s, the converter achieves 86-dB dynamic range for a 1.1-MHz bandwidth, with an average MTPR of 65 dB.

A CMOS oversampled DAC with multi-bit semi-digital filtering and boosted subcarrier SNR for ADSL central office modems

A 0.6 um CMOS analog front end IC supporting ADSL central office and remote terminal (category I and II) modem applications is developed. The receive path contains a low-noise programmable gain amplifier, analog equalizer, antialiasing filter, and a 12 bit A/D converter. The transmit channel incorporates a 14 bit D/A converter and a low-pass filter. The IC consumes 525 mW on a 5 V supply.

Analog front end IC for category I and II ADSL

A central office ADSL-VDSL line driver in a 0.35 /spl mu/m 3.3 V CMOS technology is presented. The chip has a missing tone power ratio (MTPR) over 55 dB driving ADSL signals and can deliver VDSL downstream signals with a bandwidth of 8.6 MHz and an out-of-band PSD of -103 dBm/Hz. The power efficiency is 47% for 100 mW ADSL signals with a crest factor of >5.

https://ieeexplore.ieee.org/iel5/7911/21814/01012763.pdf

A central office combined ADSL-VDSL line driver solution in .35/spl mu/m CMOS

An analog-front-end design including the power-management circuits to achieve an SoC ADSL CPE modem solution is presented. The integrated AFE with less than 2nV//spl radic/Hz input referred noise, dynamically adaptive hybrid and combination of the analog and digital filtering provides a single-chip solution.

A 0.13/spl mu/m CMOS four-channel ADSL2+ analog front-end for CO applications with 75mW per channel

Asymmetrical digital subscriber line (ADSL) provides robust transport of data at up to 8 Mb/s on common twisted pair without interfering with classical telephone service. ADSL uses multicarrier modulation (DMT) to modulate up to 256 QAM into a 1.104 MHz frequency band, which requires a signal path with at least 66 dB of dynamic range for full performance. The circuit described operates either as ATU-C (central office) or as ATU-R (customer premises) ADSL analog front-end by swapping upstream and downstream filters.

F. Louagle

Papers

A 0.5 /spl mu/m CMOS ADSL analog front-end IC