A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Programmable logic array integrated circuits

This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.

Customizable and programmable cell array

A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.

Programmable interconnect architecture

An improved programmable logic cell (1) for use in a programmable logic array comprising cells which are arranged in two-dimensional matrix of rows and columns and are interconnected by a two-dimensional array of direct connections between a cell (1) and its four nearest neighbors, one to its left (or to the West) (3a, 3b, 7a, 7b) and one to its right (or to the East) (5a, 5b, 9a, 9b), one above it (or to the North) (2a, 2b, 6a, 6b) and one below it (or to the South) (4a, 4b, 8a, 8b). Each cell receives input (s) from each of its nearest neighbors and additional input(s) from a bus, pin, or neighbor and may be programmed to generate a variety of logical functions at its outputs which connect to the cell's four nearest neighbors. The core of the improved logic cell (fig.2) comprises two upstream gates (21, 23) the outputs of which feed two downstream gates (28, 41), one of which is an exclusive-OR gate (28) which feeds a downstream register (33). Additional programmable connections and other logic augment the cell core to produce cell embodiments which can be configured to efficiently implement various logical functions. Among the functions which may be implemented by the improved cell are a number of two-level combinational functions (such as multiplexing) and sequential functions (such as counting and shifting). A variety of cell embodiments based on the improved cell core are illustrated.

Programmable logic cell and array

A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Programmable logic element interconnections for programmable logic array integrated circuits

A laser programmable integrated circuit chip has a plurality of logic modules organized as rows and columns. The modules and other chip components are connected by a grid-like array of conductors. The conductors are initially unattached. Customization occurs by fusing laser diffuseable links and severing cut points on the conductors. The modules have continuous conductor lines running through them. These conductor lines aid in testing and are useful in routing and error avoidance. The chip also contains test registers to test the array of logic modules, the input/output blocks, and the conductors.

F. Matthew Rhodes

Papers

Laser programmable integrated circuit