IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

System-on-Chip: Reuse and Integration

In this study we discuss the problem of Model Order Reduction (MOR) for a class of nonlinear dynamical systems. In particular, we consider reduction schemes based on projection of the original state-space to a lower-dimensional space e.g. by using Krylov methods. In the nonlinear case, however, applying a projection-based MOR scheme does not immediately yield computationally efficient macromodels. In order to overcome this fundamental problem, we propose to first approximate the original nonlinear system with a weighted combination of a small set of linearized models of this system, and then reduce each of the models with an appropriate projection method. The linearized models are generated about a state trajectory of the nonlinear system corresponding to a certain ‘training’ input. As demonstrated by results of numerical tests, the obtained trajectory quasi-piecewise-linear reduced order models are very cost-efficient, while providing superior accuracy as compared to existing MOR schemes, based on single-state Taylor’s expansions. In this dissertation, the proposed MOR approach is tested for a number of examples of nonlinear dynamical systems, including micromachined devices, analog circuits (discrete transmission line models, operational amplifiers), and fluid flow problems. The tests validate the extracted models and indicate that the proposed approach can be effectively used to obtain system-level models for strongly nonlinear devices. This dissertation also shows an inexpensive method of generating trajectory piecewise-linear (TPWL) models based on constructing the reduced models ‘on-the-fly’, which accelerates simulation of the system response. Moreover, we propose a procedure for estimating simulation errors, which can be used to determine accuracy of the extracted trajectory piecewise-linear reduced order models. Finally, we present projection schemes which result in improved accuracy of the reduced order TPWL models, as well as discuss approaches leading to guaranteed stable and passive TPWL reduced-order models. Thesis Supervisor: Jacob K. White Title: Professor of Electrical Engineering and Computer Science

/pdf/a-trajectory-piecewise-linear-approach-to-model-order-26i7es0r5o.pdf

A trajectory piecewise-linear approach to model order reduction of nonlinear dynamical systems

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

https://spectrum.library.concordia.ca/977369/1/MEJ%2D2008.pdf

Review: Formal verification of analog and mixed signal designs: A survey

The electronics industry is increasingly focused on the consumer marketplace, which requires low-cost high-volume products to be developed very rapidly. This, combined with advances in deep submicrometer technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixed-signal (MS) systems-on-chip presents enormous challenges both to the designers of the chips and to the developers of the computer-aided design (CAD) systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large single-chip MS systems and how CAD systems are expected to develop to overcome these issues.

/pdf/design-of-mixed-signal-systems-on-a-chip-1ase6umq8j.pdf

F. Sendig

Papers

Design of mixed-signal systems-on-a-chip