A 8 b-wide single-ended simultaneous bidirectional transceiver test chip in a 0.4 /spl mu/m CMOS process allows study of the major challenges in high-performance, low-cost parallel-link design. This paper shows the I/O cell and placement of I/O pads in each chip. Data pins are laid out with different signal return configurations to study cross-talk in parallel links. In the I/O cell, the open-drain output driver is broken down into 4 legs ratioed 1:2:4:4 for swing control. The line is terminated on each side with a pMOS resistor, whose gate voltage is adjusted externally for impedance control. Two externally-adjustable reference voltages (VrefH and VrefL) are multiplexed to generate the local reference voltage (Vref) to decode incoming data. The I/O design operates at a bit time equal to 4 fanout-of-4 delays (FO4=delay of an inverter driving a load of 4 identical inverters and is 193 ps at a 3.3 V supply in this run). The bidirectional links operate at 2.4 Gb/s/pin (1.2 Gb/s in each direction), with 200 mV minimum signal swing on each side for the pins with worst-ease cross-talk.

A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensation

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

A master/slave system architecture including a single wire bus and master device and bus interface coupled to the bus. The system further includes slave devices having respective bus interfaces coupled to the bus. The system further includes a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions for communicating between the master and the slave devices. The communication protocol further includes Master Slave Operational Interface (MSOI) that includes repertoire of functions properties stored in the master device, whereby, the master can communicate with any slave device that supports functions properties that belong to the repertoire of functions properties, using the bus transactions, substantially without need of retrofit.

Single wire bus for connecting devices and methods of operating the same

Inter-chip interconnect has become increasingly important due to the recent rapid development of switch fabric data network and symmetric multi-processing (SMP) server technologies. A high-speed parallel data transceiver megacell has low power, latency, and pin count for point-to-point interconnect between chips. Each macro includes a transmitter and a receiver. The aggregate bandwidth is 32 Gb/s, or 16 Gb/s in each direction. An on-chip timing calibration circuit performs data de-skewing and timing optimization. A transport layer handles error correction through the link. Low swing differential signaling further reduces noise and error probability, and therefore relaxes restrictions of board design. The entire macro is portable and scalable, and can be integrated with standard logic process. It also works well with standard packages such as EGA or QFP. Built-in self test (BIST) logic is implemented for product testing.

A scalable 32 Gb/s parallel data transceiver with on-chip timing calibration circuits

Simultaneous bi-directional transceiver logic (SBTL) doubles data bandwidth because data are transmitted simultaneously in each direction over one wire. The technique has enhanced the cost performance of a commercial high-end UNIX server because the number of LSI signal pins, board signal nets, and connectors have decreased by half. And the SBTL speed can improve to more than 1 Gb/s per pin by using advanced process and circuit technology. The previous high frequency interface uses source-synchronous transmission. But a transmission that is not synchronized with a system clock requires long latency time of several cycles for clock synchronization and data recognition at the receiver LSI. A large interface circuit for the clock synchronization is a disadvantage. Therefore, the SBTL technique synchronized with a system clock has been developed in this work to minimize the latency time even at a high frequency of 1.1 Gb/s per pin. Also, a high-speed signal pin count per LSI is important. Low-noise technique of an output buffer circuit and a package has been developed to get a 100 B high-speed data bus per LSI. The maximum data bandwidth is 110 GB/s per LSI.

F. Shirotori

Papers

110 GB/s simultaneous bi-directional transceiver logic synchronized with a system clock