Design of a Dynamic ADC Comparator with Low Power and Low Delay Time for IoT Application

We study synchronization in networks of delay-coupled electronic oscillators, so-called phase-locked loops (PLLs). Using a phase-model description, we study the collective dynamics of mutually coupled PLLs and report the phenomenon of heterogeneity-induced synchronization. This phenomenon refers to the observation that heterogeneity in the system's parameters can induce synchronization by stabilizing the states which are unstable without such heterogeneity. In systems where component heterogeneity can be tuned and controlled, we show how the complex collective self-organized dynamics can be guided towards synchronized states with specific operational frequencies and phase relations. This is of importance for the technical applicability of self-organized dynamics. In electrical engineering, for example, where components can be strongly heterogeneous, our theoretical framework can inform the design process for networks of spatially distributed PLLs. The results presented here are also useful in understanding the collective dynamics in ensembles of phase oscillators with time-delayed interactions, inertia, and heterogeneity.

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Heterogeneity-induced synchronization in delay-coupled electronic oscillators.

In this article, we propose a matching network design algorithm based on the segmentation of the real and imaginary part of optimum source impedance curve with respect to space variable x and frequency ω , respectively. The impedance curve (comprising of real and imaginary parts) is approximated as a collection of n linear segments, represented by the weighted sum of n semi‐infinite linear functions. Using the numerical method, optimum weight vectors that maximize transducer power gain are obtained to model the real and imaginary parts of the source impedance curve. We get the values of optimum weight vectors and the rational input impedance function for the matching network, which are then synthesized in the desired topology by a continued partial fraction. Experimentally, we validate the novelty of the proposed method by designing matching networks of a wideband custom monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) in 1.3–2.3 GHz frequency band. The measured results of the designed LNA are significantly close to the simulated results. We bias our LNA at (5 V, 150 mA) and achieve a maximum noise figure of 1.25 dB, OP1dB of 26 dBm, and an average TOI of 38 dBm. Moreover, our design of custom LNA MMIC has an integrated ESD structure while occupying only 0.32 mm2 of chip area.

A multi‐variable double impedance matching network design algorithm with design example of a low noise amplifier

True-time delay (TTD) cells are used in timed array receivers for wideband multi-antenna topologies. TTD cells are divided into two major categories: silicon-based and non-silicon-based structures. Non-silicon-based structures have very good bandwidth but are bulky in the below 10 GHz frequency band. Silicon-based TTD cells are much more compact and better candidates for integrated circuit (IC) design. Passive and active approaches are the two ways to have a silicon-based TTD cell. Passive TTD cells are built by transmission lines (TL), artificial transmission lines (ATL), and LC ladder networks. Their power consumption is very low, and the delay bandwidth is good, but they are still bulky at low frequencies like below 5 GHz applications. Active all-pass filters as TTD cells are presented for these issues. In this chapter, we will discuss the challenges of inductor-based TTD cells. Then, inductor-less TTD cells are presented to address some of the previous structure’s issues. Finally, we will talk about these structures’ challenges as well. Then, the nonidealities effects on the TTD cell’s performance are investigated, and the body bias technique is presented to address these issues. 

Wideband True Time Delay Cells

Design of high gain high output matched narrow band LNA using induced degeneration topology for receiver applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with gm boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a new compensation technique for the low noise amplifier (LNA) with the high capability and efficiency for low power applications is proposed. The supply voltage and bias of the LNA are near the sub-threshold voltage, which has excellent effect on reducing power consumption. At this voltage level, the gain decreases and the various circuit parameters become extremely sensitive to process, voltage and temperature (PVT) changes. To overcome the problem, a compensating circuit with variable current source to control the LNA bias voltage is used. The output of the compensator circuit is adjusted according to changes in temperature, voltage and five process corners, and produces a variable voltage. The temperature compensator consists of two current sources that produce a current proportional to temperature changes. Regarding process and voltage compensator, according to the state created in the circuit, the appropriate amount of current is injected through the output and finally stabilizes the main parameters of the LNA circuit. In LNA circuit, for proper performance at supply voltage near the sub-threshold and attaining the gain improvement, forward body bias and gm-boosting techniques are employed, respectively. The LNA circuit along with the PVT compensator at supply voltage of 0.35V, consumes about 567µW power consumption that here 91µW is caused by the PVT compensator circuit. In the proposed circuit, the rate of noise figure (NF) and gain (S21) changes compared to temperature changes in the five corners have decreased by 4.3 and 12.1 times versus LNA with constant bias, respectively. In this case, with 20% changes of VDD, NF and S21 changes decreased by 23 and 11.35 times, respectively. The results are provided by Cadence software using 65nm CMOS technology.

PVT-Compensated Low Voltage LNA Based on Variable Current Source for Low Power Applications

Introduction: Diabetes is one of the most common chronic diseases in the world that occurs at the time of disasters and its complications are aggravated. Therefore, developing a comprehensive plan seems necessary to care for diabetic patients in disasters. Objectives: This study aimed to develop the elements of a curriculum for nurses regarding diabetic patients’ care in disasters. Materials and Methods: This was a multi-stage quantitative study in which 380 nurses working in the Armed Forces hospitals in Tehran, Iran, in 1399 participated, who were selected through convenience sampling. The study units reported their educational needs to provide services to diabetic patients in disasters in a valid and reliable researcher-made questionnaire with 72 items using the self-assessment method. According to the needs assessment results, the curriculum elements were presented based on a six-step process. The Delphi method was utilized in two rounds to determine the desirability of the program. The statistical sample at this stage was 10 expert professors selected through snowball sampling. Finally, the developed curriculum was reviewed, revised, and approved in an expert roundtable session. Data were analyzed using the SPSS software (version 22). Results: The results of the educational needs assessment of nurses regarding diabetic patients’ care in disasters were identified in the form of 9 tasks, 19 sub-tasks, and 72 minor tasks. According to the needs assessment and international experience, the elements of the disaster care curriculum were developed, and their desirability was approved by experts in two rounds using the Delphi method. Conclusion: The developed program can be effective in guiding nurses to provide care to diabetic patients in disasters. It is suggested that the program developed in this study be presented at regular intervals in the form of in-service retraining programs for nurses. 

Fatemeh Zaheri

Papers

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

PVT-Compensated Low Voltage LNA Based on Variable Current Source for Low Power Applications

Curricula development of diabetic patients care in disasters for nurses