Quantum-dot cellular automata (QCA) is an emerging nanotechnology, with the potential for faster speed, smaller size, and lower power consumption than transistor-based technology. Quantum-dot cellular automata has a simple cell as the basic element. The cell is used as a building block to construct gates and wires. Previously, adder designs based on conventional designs were examined for implementation with QCA technology. That work demonstrated that the design trade-offs are very different in QCA. This paper utilizes the unique QCA characteristics to design a carry flow adder that is fast and efficient. Simulations indicate very attractive performance (i.e., complexity, area, and delay). This paper also explores the design of serial parallel multipliers. A serial parallel multiplier is designed and simulated with several different operand sizes.

Adder and Multiplier Design in Quantum-Dot Cellular Automata

The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations on reduction of QCA primitives (majority gates and inverters) for various adders are limited. In this paper, we present a number of new results on majority logic. We use these results to present efficient QCA designs for the ripple carry adder (RCA) and various prefix adders. We derive bounds on the number of majority gates for -bit RCA and -bit Brent-Kung, Kogge-Stone, Ladner-Fischer, and Han-Carlson adders. We further show that the Brent-Kung adder has lower delay than the best existing adder designs as well as other prefix adders. In addition, signal integrity and robustness studies show that the proposed Brent-Kung adder is fairly well-suited to changes in time-related parameters as well as temperature. Detailed simulations using QCADesigner are presented.

Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA

A novel design of 8-bit adder/subtractor by quantum-dot cellular automata

Here is the first book devoted to quantum-dot cellular automata (QCA) - an emerging nanoelectronic circuit design technology that more and more industry experts are viewing as a superior alternative to current technologies. QCA promises to help practitioners achieve room temperature operation and realize improvements in speed, density and power over existing (CMOS) systems. This groundbreaking resource provides a comprehensive view of QCA, showing practitioners how to work with this cutting-edge technology. The book offers an in-depth understanding of the design, test, defect tolerance, and computer aided design support for QCA. It identifies and discusses the key challenges facing QCA and offers possible solutions to these issues. Additionally, professionals find a comprehensive nanotechnology survey, detailing the advantages and disadvantages of various technologies.

Design and Test of Digital Circuits by Quantum-Dot Cellular Automata

This paper first presents an efficient quantum-dot cellular automata (QCA) design for the Ladner-Fischer prefix adder. We then present an efficient QCA design of a hybrid adder that combines the Ladner-Fischer adder with a ripple carry adder. We show that the hybrid adder has better performance (in terms of latency) in QCA than a Ladner-Fischer or a ripple carry adder. We also show that the hybrid adder has a smaller area-delay product than existing adder designs in QCA. Results of simulation in QCADesigner are also given and they support the theory presented.

Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata

SET-based nano-circuit simulation and design method using HSPICE

This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. A full-adder is designed with QCA cells using the SPICE model as a test vehicle and the function is verified successfully. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE.

Quantum-dot cellular automata SPICE macro model

In order to design large digital circuits using quantum-dot cellular automata (QCA) cells, CAD tools and automated design methodology for QCA circuits are essential. This paper presents a QCA circuits design methodology based on traditional CMOS circuit design flow. This QCA circuit design methodology utilizes the current CMOS circuit design tools such as HSPICE and Synopsys design compiler. The QCA cell SPICE model is built for timing checking and accurate simulation. The basic QCA layout algorithm is developed for placing the QCA cells in the proper clock zones. A full adder design is shown as an example to demonstrate the whole design process.

QCA-based nano circuits design [adder design example]

The objective of this paper is to provide a framework by which jitter, in the output signals of a test-head board in an automatic test equipment (ATE), can be measured. In this paper, jitter phenomena caused by radiated electromagnetic interference (EMI) noise are considered. EMI noise is mainly present in the test head of an ATE as result of the activity of the dc-dc converters. An analysis has been pursued to establish the areas of the test-head board that are most sensitive to EMI noise. The most sensitive part of the test-head board has been found to occur in the loop filter of the phase-locked loop (PLL) that is used to obtain a high-frequency clock for the timing generator (TG). Different H-fields are then externally applied to the loop filter to verify the behavior of the output signal in terms of rms jitter. A frequency-domain methodology has been employed for the rms-jitter measurements. The rms-jitter variation for the radiated EMI magnitude and frequency has been characterized. Also, the orientation of the external H-field source has been investigated with respect to the target board and its effects on the measured rms jitter. For measuring the jitter, an interface circuitry has been designed on an adapter board to circumvent ground noise and connectivity problems arising from the test-head environment.

Measuring the timing jitter of ATE in the frequency domain

This paper presents a simulation and design method for complementary SET-based nano-circuits. A HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth-Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows a reduced CPU time and more compatibility with other SPICE softwares on both Windows and Unix. The design methodology illustrates how to build CMOS-like SET circuits, and based on it, conventional static CMOS circuit design methodologies are all applicable to SET circuit designs. Simulation results show that, for 1M$\Omega$ junction resistance, the power consumption of a SET NAND2 gate is less than 0.3pW, and the propagation delay for a SET XOR2 gate is only 29.8ns while driving a 10aF load.

Fengming Zhang

Papers

SET-based nano-circuit simulation and design method using HSPICE

Quantum-dot cellular automata SPICE macro model

QCA-based nano circuits design [adder design example]

Measuring the timing jitter of ATE in the frequency domain

SET-based nano-circuit simulation and design method using HSPICE