This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

This work presents and analyzes the design of a 1-V ultra-low power, compact, and wideband low-noise amplifier (LNA). The proposed LNA uses common-gate (CG) NMOS and PMOS transistors as input devices in a complementary current-reuse structure. Low power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor to improve the current efficiency of the LNA. A forward body biasing (FBB) scheme is exploited to tune the feedback coefficient. The complementary characteristics of the input stage leads to partial second-order distortion cancellation. The proposed inductorless LNA is implemented in an IBM 0.13- $\mu {\text {m}}~1$ P8M CMOS technology and occupies only $0.0052~{\text {mm}}^{2}$ . The measured LNA has a 12.3-dB gain 4.9-dB minimum noise figure (NF) input referred third-order intercept point (IIP3) of −10 dBm and 0.1–-2.2 GHz bandwidth (BW), while consuming only 400 $\mu {\text {A}}$ from a 1-V supply.

An Ultra-Low-Power Wideband Inductorless CMOS LNA With Tunable Active Shunt-Feedback

This work examines the use of a forward body biasing (FBB) scheme to mitigate output conductance degradation due to short channel effects in ultra-low voltage (ULV) circuits with no additional power consumption. It is shown that FBB boosts the output resistance of a transistor such that the intrinsic gain reduction due to low-supply voltages can be compensated. This technique is then used to implement a low-noise amplifier (LNA) tailored for ultra-low power (ULP) and ULV applications. The proposed LNA uses common-gate (CG) NMOS transistors as input devices in a complementary current-reuse structure. Low-power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor. Moreover, a separate FBB scheme is exploited to tune the feedback coefficient. An inductive $g_m$ -boosting technique is used to increase the bandwidth of the LNA without additional power consumption. The proposed LNA is implemented in an IBM $0.13\ \upmu \text{m}$ 1P8M CMOS technology and occupies $0.39\ \text{mm}^2$ . The measured LNA has a 14 dB gain, 4 dB minimum noise figure, IIP3 of $-10\ \text{dBm}$ , and 0.6–4.2 GHz bandwidth, while consuming only $500\ \upmu$ A from a 0.5 V supply. The LNA operates with supplies as low as 0.4 V while maintaining good performance.

Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 $\upmu \text{W}$ 0.6–4.2 GHz Current-Reuse CMOS LNA

Future hyper-connected devices must support several communication standards, across various frequency bands, with a low-area, single-chip, radio frequency frontend. In this paper, we present a reconfigurable, inductorless, wideband, low-noise amplifier (LNA) for multistandard applications. This LNA is based on a complementary current-reuse common source amplifier, combined with a low-current active feedback. A gyrator-C effect is used to achieve wideband input matching. High linearity is obtained through complementary derivative superposition and active shunt feedback. Implemented in 130-nm CMOS technology, the prototype exhibits a -3 dB bandwidth of 2.2 GHz. In high linearity mode, the LNA achieves a minimum $NF$ of 2 dB, a voltage gain of 21.1 dB and an $IIP_{3}$ of +14.3 dBm, with 7 mW of power consumption. In low-power mode, it draws 1.5 mW, while providing a NF of 2.6 dB, a gain of 21 dB, and an $IIP_{\mathrm {3}}$ of 4.7 dBm. The active die area is 0.0072 mm2.

Reconfigurable Inductorless Wideband CMOS LNA for Wireless Communications

This paper presents a low-power transceiver with a reconfigurable sliding-IF (intermediate frequency) architecture targeted for wireless body area networks hubs covering 400 MHz and 2.4 GHz bands. By using this architecture, a 1608-1988 MHz PLL synthesizer with only 21% tuning range can fully cover all the available bands around 400 MHz and 2.4 GHz as defined by IEEE 802.15.6 NB (narrow band) and ZigBee. The dual-band transceiver has been designed in 0.18 μm CMOS process. The design consists of a receiver with a wideband front-end and a reconfigurable amplifier-mixer, a transmitter with a reconfigurable two stage full quadrature mixer, a ΣΔ fractional-N PLL and some auxiliary circuits. The measurement result has demonstrated that the proposed transceiver can satisfy the dual-band requirements with comparable or even better performance in noise, receiver sensitivity and power consumption compared to previously-reported transceivers for only a single band.

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several g m -enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic g m of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP 3 is ―12 dBm for an input compression point of —21 dBm.

A Low Power Inductorless LNA With Double Gm Enhancement in 130 nm CMOS

This paper presents an inductorless low power (LP) low noise amplifier (LNA) based on a Common Gate (CG) topology. The circuit combines gain boosting techniques to enable high gain LP LNA. The circuit is integrated in a 130nm CMOS technology and shows 20dB gain with 4dB Noise Figure and −12dBm IIP3. The power consumption is 1.32mW from a 1.2V supply.

A 1.3mW 20dB gain low power inductorless LNA with 4dB Noise Figure for 2.45GHz ISM band

In this paper we present a new method for controlling the performance of a Differential Active Inductor (DAI) used as resonating output load of an RF amplifier and working at Ultra Low Power (ULP) consumption. A new solution is proposed for linearity improvement without extra power consumption and without SNR degradation. For a given impedance value at the resonance frequency of the DAI (corresponding to a given amplifier gain), tradeoff between quality factor Q and IIP 3 is highlighted. Then, an optimization method is proposed which takes into account the power consumption. A simulated DAI presents -2.7 dBm IIP 3 , 40nV/Hz noise voltage density and almost 3.0kΩ load at the resonance frequency of 2.45GHz. The total power consumption is 0.8 mW under 1V power supply of a 65nm CMOS technology, and the circuit occupies 0.0012 mm² of silicon area.

Francois Belmas

Papers

A Low Power Inductorless LNA With Double Gm Enhancement in 130 nm CMOS

A 1.3mW 20dB gain low power inductorless LNA with 4dB Noise Figure for 2.45GHz ISM band

A new method for performance control of a differential active inductor for low power 2.4GHz applications