Described are methods of making silicon nitride (SiN) materials on substrates. Improved SiN films made by the methods are also included. One aspect relates to depositing chlorine (Cl)-free conformal SiN films. In some embodiments, the SiN films are Cl-free and carbon (C)-free. Another aspect relates to methods of tuning the stress and/or wet etch rate of conformal SiN films. Another aspect relates to low-temperature methods of depositing high quality conformal SiN films. In some embodiments, the methods involve using trisilylamine (TSA) as a silicon-containing precursor.

Method for depositing a chlorine-free conformal SiN film

Methods for depositing conformal films using a halogen-containing etchant during atomic layer deposition are provided. Methods involve exposing a substrate to a halogen-containing etchant such as nitrogen trifluoride between exposing the substrate to a first precursor and exposing the substrate to a second plasma-activated reactant. Examples of conformal films that may be deposited include silicon-containing films and metal-containing films. Related apparatuses are also provided.

Deposition of conformal films by atomic layer deposition and atomic layer etch

Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays

A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash. The method includes determining a data value from one of more than two data values to be stored in the memory cell, and applying a gate voltage to the control gate at one of a predetermined set of gate voltage levels selected in response to the determined data value. Programming parameters are controlled to establish a self-converging threshold state that is determined by the selected gate voltage. In this manner, the threshold voltage converges on a target threshold corresponding with the determined data value for the memory cell. Program verify operations are reduced or eliminated in various embodiments, reducing the overall time required for the program operation, and improving device performance. A second portion of the program operation can include verify operations to improve threshold margins across the array.

Operation scheme for programming charge trapping non-volatile memory

Disclosed herein are methods of depositing a SiN film having a reduced wet etch rate. The methods may include adsorbing a film precursor comprising Si onto a semiconductor substrate in a processing chamber to form an adsorption-limited layer of precursor, and then removing unadsorbed precursor from the volume surrounding the adsorbed precursor. The adsorbed precursor may then be reacted by exposing it to a plasma comprising N-containing ions and/or radicals to form a SiN film layer on the substrate, and the SiN film layer may then be densified by exposing it to a He plasma. The foregoing steps may then be repeated to form another densified SiN film layer on the substrate. Also disclosed herein are apparatuses for depositing SiN films having reduced wet etch rates on semiconductor substrates which employ the foregoing techniques.

Methods and apparatuses for uniform reduction of the in-feature wet etch rate of a silicon nitride film formed by ALD

A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102 ), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104 ), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106 ).

Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices

According to one embodiment, a nonvolatile storage circuit ( 100 ) can include a volatile portion ( 102 ) that includes p-channel metal-oxide-semiconductor (MOS) transistors ( 106 - 0 and 106 - 1 ) and n-channel MOS (NMOS) transistors ( 108 - 0 and 108 - 1 ) arranged in a complementary MOS (CMOS) latch configuration. Also included are nonvolatile devices ( 116 - 0 and 116 - 1 ) disposed between PMOS transistor 106 - 0 and NMOS transistor 108 - 0 , and between PMOS transistor 106 - 1 and NMOS transistor 108 - 1 . Nonvolatile devices ( 116 - 0 and 116 - 1 ) can include silicon-oxide-nitride-semiconductor (SONOS) transistors that can be programmed to opposite states to recall a logic value when power is applied to the nonvolatile storage circuit ( 100 ). In a read mode, a bias voltage VBIAS can be applied to nonvolatile devices ( 116 - 0 and 116 - 1 ) that tends to retain charge in both nonvolatile devices ( 116 - 0 and 116 - 1 ).

Silicon-oxide-nitride-oxide-semiconductor (SONOS) type memory cell and method for retaining data in the same

A semiconductor device and method of manufacturing a semiconductor device is disclosed in which a SONOS-type dielectric may include a charge storing dielectric (206) that includes at least one charge trapping dielectric layer (212) formed within. A charge trapping dielectric layer (212) may be a silicon-rich silicon nitride layer that may trap charge that could otherwise tunnel through a charge storing dielectric (206). A method may include forming a tunneling dielectric (302), forming a first portion of a charge storing layer (304-0), forming a charge trapping layer (306), forming a second portion of a charge storing layer (304-1), and forming a top dielectric (308).

Semiconductor device having silicon-rich layer and method of manufacturing such a device

A CMOS semiconductor device which avoids latchup in the powerup mode as well as in the normal operating mode is provided. The device is provided with an on-chip back bias generator which greatly reduces the possibility of forward biasing parasitic NPNP transistors in normal operation. During the powerup mode, before the backbias voltage becomes effective, a clamp diode provided in integrated form outside a guardring surrounding the circuit elements is effective to clamp a large negative voltage that may be created by a "hot-socket" connection to an output. In a modified form of the invention, a junction field effect transistor is provided to prevent forward biasing of the parasitic transistors in a somewhat different manner.

Fred Jenne

Papers

Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices

Silicon-oxide-nitride-oxide-semiconductor (SONOS) type memory cell and method for retaining data in the same

Semiconductor device having silicon-rich layer and method of manufacturing such a device

Back biased CMOS device with means for eliminating latchup