In a phase-locked loop with reference, feedback, and error signals, the trade-off between lock-up time and power dissipation is improved by one of the following methods: supplying a continuous error signal, instead of an intermittent error signal, to a charge pump during lock acquisition; employing a half-integer frequency divider and making multiple phase-and-frequency comparisons during each reference signal cycle; employing a prescaled feedback signal and making multiple phase-and-frequency comparisons during each reference signal cycle; providing multiple feedback loops and employing a selectable number of the loops during lock acquisition; and employing multiple feedback loops with prescaling of the reference and feedback signals.

Phase-locked loop with improved trade-off between lock-up time and power dissipation

A clock signal generation apparatus includes a first device for extracting reference information from an input digital signal. An oscillator operates for generating a reference clock signal having a frequency depending on a control signal. A second device connected to the first device and the oscillator operates for generating the control signal to the oscillator in response to the reference clock signal generated by the oscillator and the reference information extracted by the first device, and for locking a phase of the reference clock signal to the reference information. A third device connected to the second device operates for deciding whether or not the phase of the reference clock signal is successfully locked to the reference information. A fourth device connected to the second device, a memory, and the third device operates for storing the control signal generated by the second device into the memory when the third device decides that the phase of the reference clock signal is successfully locked to the reference information. A fifth device connected to the memory, the oscillator, and the second device operates for selecting one of the control signal currently generated by the second device and the control signal stored in the memory, and for feeding the selected control signal to the oscillator.

Clock signal generation apparatus

A circuit device includes an oscillation signal generation circuit, a reference signal input terminal to which a reference signal is input, and an internal phase comparator that performs phase comparison between an input signal based on the oscillation signal and the reference signal. The oscillation signal generation circuit generates the oscillation signal using the frequency control data based on a result of the phase comparison from an external phase comparator which performs phase comparison between an input signal based on the oscillation signal and the reference signal in a first mode, and generates the oscillation signal using the frequency control data based on a result of the phase comparison from the internal phase comparator in a second mode.

Circuit device, oscillator, electronic apparatus, and vehicle

A phase locked loop (PLL) circuit includes a first signal detector having a first input terminal configured to receive a varying first input signal, a second input terminal configured to receive a feedback signal that corresponds to the center of the input frequency, and an output terminal configured to provide an output signal corresponding to a phase difference between the first input and feedback signals. A delay estimator has an input terminal configured to receive the output signal from the first phase detector and in response thereto, output a phase difference estimation signal. A variable delay circuit has an input terminal configured to receive the phase difference estimation signal and in response thereto, phase shift the second input signal.

Predictive phase locked loop system

A phase-locked loop includes: a voltage-controlled oscillator (VCO) system receiving one or more control signals and in response thereto generating a PLL output signal; a plurality of phase detectors for comparing a reference signal having a reference frequency to a PLL feedback signal having a PLL feedback frequency derived from the PLL output signal, and in response thereto to output a comparison signal; and a plurality of signal processing paths each connected to an output of a corresponding one of the phase detectors for outputting a phase detection output signal. The signal processing paths have different frequency responses from each other. In operation only one of the phase detectors is activated, and a switching arrangement selectively switches between outputs of the signal processing paths to select the phase detection output signal from the activated phase detector to generate the control signal(s) for the VCO system.

Phase- locked loop with switched phase detectors

A first phase comparator 22 of digital type and a second phase comparator 32 of sampling type are provided. Near a lock phase, an output current Iout2 is fed from the second phase comparator 32 to a voltage-controlled oscillator 14 through a change-over switch 40. In other phases, an output current Iout1 is fed thereto from the first phase comparator 22. When a reference signal fs is missing, a complementing circuit 50 complements a pulse to at least the reference signal fs input to the first phase comparator 22. A noise detecting/removing circuit 60 detects and removes noise from the reference signals fs, permits the reference signals fs to be fed to the first and second phase comparators 22 and 23, and halts the operations of the two phase comparators 22 and 32 for only a predetermined period of time after the noise has been detected. Therefore, the PLL circuit stably operates and characters are clearly displayed on a screen even when the noise is contained in the horizontal synchronizing signals of the video signals or even when the signals are missing.

Phase locked loop circuit and a picture reproducing device

A digital first phase comparator (22) and a sampling type second phase comparator (32) are provided in parallel. The output current Iout2 of the comparator (32) is inputted to a voltage-controlled oscillator (14) when the phase is close to a locked phase. In the other phase, the output current Iout1 of the comparator (22) is inputted to the oscillator (14). When part of a reference signal fs is lost, a complementing circuit (50) complements at least the reference signal fs inputted to the comparator (22) by pulses. A noise detecting and removing circuit (60) detects and removes the noise of the signal fs and inputs the signals fs to the comparators (22 and 32). The circuit (60) stops the operation of the comparators (22 and 32) for a prescribed period of time after detecting the noise. Therefore, the operation of a PLL circuit is stabilized and characters can be displayed sharply on a screen even when the horizontal synchronizing signal of video signals contains noise or part of the signal is lost.

Fumihiro Takahashi

Papers

Phase locked loop circuit and a picture reproducing device

Pll circuit and picture reproducing device