An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

High-voltage lateral transistor with a multi-layered extended drain structure

In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region of a first conductivity type, a gate trench which extends into the first semiconductor region, and a source trench which extends into the first semiconductor region. The source trench is laterally spaced from the gate trench.

Dual trench power MOSFET

A trenched DMOS transistor overcomes the problem of a parasitic JFET at the trench bottom (caused by deep body regions (57) extending deeper than the trench) by providing a doped trench (62) and extending into the surrounding drift region (54). This trench bottom implant region (70) has the same doping type, but is more highly doped, than the surrounding drift region (54). The trench bottom implant region (70) significantly reduces the parasitic JFET resistance by optimizing the trench bottom implant dose, without creating reliability problems.

High density trench DMOS transistor with trench bottom implant

A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region (44) and drain region (40). Forward conduction occurs through an inversion region between the source region (44) and drain region (40). Blocking is achieved by a gate controlled depletion barrier. Located between the source (44) and drain (40) regions is a fairly lightly doped body region (42). The gate electrode (52A), located in a trench (50A), extends through the source (44) and body (42) regions and in some cases into the upper portion of the drain region (40). The dopant type of the polysilicon gate electrode (52A) is the same type as that of the body region (42). The body region (42) is a relatively thin and lightly doped epitaxial layer grown upon a higly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

Punch-through field effect transistor

A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

Method of making punch-through field effect transistor

Method of operation of punch-through field effect transistor

A DMOS transistor structure comprising: a substrate (50); a drift region (54) overlying the substrate; a body region (56) overlying the drift region (54); a conductive gate electrode (64) extending in a trench (62) from the principal surface through the body region (56) and into the drift region (54) to a depth less than that of the body region (56), the body region including a channel portion in contact with a side of the trench (62) near the principal surface and a deep body portion (57) more heavily doped than the channel portion extending into the drift region (54) and spaced apart from a side of the trench (62); a source region (58) extending into the body region (56); and a trench bottom region (70) of the same conductivity type as and of a higher doping concentration than the drift region (54), and extending from a bottom of the trench (62) into the drift region (54) as deeply as the deep body portion (57) and spaced apart from the body region (56).

Fwu-Iuan Hshieh

Papers

High density trench DMOS transistor with trench bottom implant

Punch-through field effect transistor

Method of making punch-through field effect transistor

Method of operation of punch-through field effect transistor

Trench DMOS transistor with trench bottom implant