An efficient hardware implementation of a median filter is presented. Input samples are used to construct a cumulative histogram, which is then used to find the median. The resource usage of the design is independent of window size, but rather, dependent on the number of bits in each input sample. This offers a realisable way of efficiently implementing large-windowed median filtering, as required by transforms such as the Trace Transform. The method is then extended to weighted median filtering. The designs are synthesised for a Xilinx Virtex II FPGA and the performance and area compared to another implementation for different sized windows. Intentional use of the heterogeneous resources on the FPGA in the design allows for a reduction in slice usage and high throughput.

Novel FPGA-based implementation of median and weighted median filters for image processing

In spite of their good filtering characteristics for vector-valued image processing, the usability of vector median filters is limited by their high computational complexity. Given an N /spl times/ N image and a W /spl times/ W window, the computational complexity of vector median filter is O(W/sup 4/N/sup 2/). In this paper, we design three fast and efficient parallel algorithms for vector median filtering based on the 2-norm (L/sub 2/) on the arrays with reconfigurable optical buses (AROB). For 1 /spl les/ p /spl les/ W /spl les/ q /spl les/ N, our algorithms run in O(W/sup 4/ log W/p/sup 4/), O(W/sup 2/N/sup 2//p/sup 4/q/sup 2/ log W) and O(1) times using p/sup 4/N/sup 2/ / log W, p/sup 4/q/sup 2/ / log W, and W/sup 4/N/sup 2/ log N processors, respectively. In the sense of the product of time and the number of processors used, the first two results are cost optimal and the last one is time optimal.

L/sub 2/ vector median filters on arrays with reconfigurable optical buses

In digital image processing, the noise detection and removal are very important tasks, since they have wide applications in all fields. In recent years, the logic fabric and routing FPGAs architecture provides customers with a number of advantages. In this chapter, the performance is analysed with different FPGA processors in terms of slices, LUTs, and BRAM utilization is studied. The implemented hardware architecture with digital images plays an important role in all daily life applications, industrial applications such as image recognition, computer tomography, satellite television, space imaging, magnetic resonance imaging, etc., and also in areas of research and technology of geographical information systems and astronomy.

Study on Pipelined Parallel Processing Architectures for Imaging and Computer Vision

This paper deals with the implementation of a fast algorithm for two-dimensional weighted median filtering. Because of the vast amount of data that must be handled, the development of fast algorithms is very important. A fast running algorithm for weighted median filtering, which is based on using a histogram and updating it, is proposed. Experimental results prove the superiority of the proposed algorithm over that of finding the weighted median either by sorting with the Quick Sort or by selecting the r-th order statistic.

A fast implementation of two-dimensional weighted median filters

This paper presents a parallel algorithm for the calculation of vector median filters on mesh connected computers. A straightforward algorithm to find the vector median requires the computation of the sum of the distances (norms) of each vector to all other vectors in the filter window. By taking into account the fact that adjacent filter windows share common input samples, the computation of the common norms of adjacent windows could be done only once. In the proposed algorithm, a 2-D signal is assumed to be stored in a SIMD mesh connected computer of the same size. According to this scheme, each processing element (PE) computes some norms and the rest ones, that are required for the selection of the vector median, are received from its neighbouring PEs via the local communication channels. >

Two-dimensional vector median filters on mesh connected computers

Parallel algorithms on barrel shifter computers for a broad class of 1-D and 2-D signal operators are presented in this paper. Running max/min selection filter, moving average filter and sorting, which can be used in order statistics filtering, are examined. The proposed algorithms require a significantly smaller number of comparisons/computations per output point than the conventional ones. They are suitable to be implemented on barrel shifter computer topologies.

G. Angelopoulos

Papers

A fast implementation of two-dimensional weighted median filters

Two-dimensional vector median filters on mesh connected computers

Parallel digital signal filtering on barrel shifter computers