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Electronic System Level (ESL) design has mainstreamed --- it is now an established approach at most of the world's leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with `no links to implementation', ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. 

This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption. 

ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today.

Table of Contents
CHAPTER 1: WHAT IS ESL? 
CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL 
CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT 
CHAPTER 4: WHAT ARE THE ENABLERS OF ESL? 
CHAPTER 5: ESL FLOW 
CHAPTER 6: SPECIFICATIONS AND MODELING 
CHAPTER 7: PRE-PARTITIONING ANALYSIS 
CHAPTER 8: PARTITIONING 
CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG 
CHAPTER 10: POST-PARTITIONING VERIFICATION 
CHAPTER 11: HARDWARE IMPLEMENTATION 
CHAPTER 12: SOFTWARE IMPLEMENTATION 
CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION 
CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS 
APPENDIX: LIST OF ACRONYMS

* Provides broad, comprehensive coverage not available in any other such book 
* Massive global appeal with an internationally recognised author team 
* Crammed full of state of the art content from notable industry experts

ESL Design and Verification: A Prescription for Electronic System Level Methodology

Transceiver architecture selection: Review, state-of-the-art survey and case study

A low-power high linearity CMOS Gm-C channel select filter for WLAN/WiMAX receivers in 90-nm CMOS technology is presented. To reduce power consumption a biquad cell with simple architecture is used. A simple but efficient technique is also proposed to improve the linearity of the filter without increasing its power consumption. Coarse and fine tuning techniques are used to tune the cutoff frequency of the sixth-order Butterworth low-pass filter from 8.1 MHz to 13.5 MHz suitable for WLAN and WiMAX applications. The measurement results show an in-band IIP3 of + 22 dBm, an HD3 better than - 40 dB at 470 mVP input signal amplitude, and an input referred noise of 75 nV/√Hz at a power consumption of 4.35 mW from a 1-V supply. The differential filter occupies a chip area of 0.239 mm2 excluding pads.

A CMOS 4.35-mW +22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers

A novel mechanism for simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing. Multiple RF signals, which may be of various wireless standards, are received using one or more shared processing blocks thereby significantly reducing chip space and power requirements. Shared components include local oscillators, analog to digital converters, digital RX processing and digital baseband processing. In operation, multiple RX front end circuits, one for each desired wireless signal, generate a plurality of IF signals that are frequency multiplexed and combined to create a single combined IF signal. The combined IF signal is processed by a shared processing block. Digital baseband processing is performed on each receive signal to generate respective data outputs. Further, simultaneous full-duplex transmission and reception is performed using a single local oscillator. The phase/frequency modulation of the frequency synthesizer used in the TX is removed from the local oscillator signal for use in the receiver.

Simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing

An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in a 0.13 mum CMOS occupying 1.65 mm2 is presented. The circuit consists of an open-loop programmable-gain amplifier (PGA1), an active-Gm-RC low-pass filter (LPF), and a closed-loop programmable-gain amplifier (PGA2). The chain gain can be programmed in the range -6 divide 68 dB, while the input-referred noise (IRN) is 5 nV/radicHz. A dynamic range (DR) larger than 82 dB is achieved for a 1% total harmonic distortion (THD). The current consumption is minimized and adjusted for the different operation conditions, down to 11 mA for the full chain.

A CMOS 5 nV $/\surd $ Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN

Multimedia applications are driving wireless network operators to add high-speed data services such as EDGE (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme, etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or to reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-operability. This paper presents analog and digital base-band circuits that are able to support GSM (with EDGE), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) level.

/pdf/baseband-analog-front-end-and-digital-back-end-for-3dfjwa4a7c.pdf

G. Cesura

Papers

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals