Showing papers by "G. De Micheli published in 1988"

HERCULES-a system for high-level synthesis

Abstract: This paper presents an approach to high-level synthesis of VLSI processors and systems. Synthesis consists of two phases: behavioral synthesis, which involves implementation-independent representations, and structural synthesis, that relates to the transformation of a behavior into an implementation. We describe HERCULES, a system for high-level synthesis developed at Stanford University. In particular, we address the hardware description problem, behavioral synthesis and optimization using a method called the reference stack, and the mapping of behavior onto a structure. We present a model for control based on sequencing graphs that supports multiple threads of execution flow, allowing varying degree of parallelism in the resulting hardware. Results are then presented for three examples: MC6502, Intel8251 and FRISC, a 16-bit microprocessor.

Approaching a nanosecond: a 32 bit adder

Abstract: The authors describe a high performance 32-bit binary adder designed at Stanford University. Measurements indicate that the adder computes the sum of two numbers (and a carry) in 2.1 ns and consumes 900 mW, using a power-supply voltage of -4.5 V. The adder is implemented using silicon emitter-coupled-logic circuitry with 0.5-V output swings. The high performance is a result of high-speed logic/technology and a special addition algorithm which results in an adder with a maximum of three levels of logic from any input to any output. The maximum fanout on any signal is eight input loads, the maximum number of inputs on any gate is five, and the maximum number of WIRE-OR outputs is eight. >