A new technique to de-embed the contributions of parasitic structures from transmission line measurements is presented and applied to microstrip lines fabricated in 90- and 130-nm RF-CMOS technologies. De-embedded measurements are used to extract characteristic impedance, attenuation constant, group delay, and effective permittivity. The effective thickness of the ground plane is demonstrated to be as important as the thickness of the top metal layer in minimizing interconnect loss. Furthermore, it is confirmed that metal area densities as low as 65% are adequate for the ground plane of microstrip lines.

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De-embedding transmission line measurements for accurate modeling of IC designs

This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The transceiver has been fabricated in a standard 65-nm CMOS process. It in cludes a receiver with a 17.3-dB conversion gain and less than 8.0-dB noise figure, a transmitter with a 18.3-dB conversion gain, a 9.5-dBm output 1 dB compression point, a 10.9-dBm saturation output power and 8.8-% power added efficiency. The 60-GHz frequency synthesizer is implemented by a combination of a 20-GHz PLL and a 60-GHz quadrature injection-locked oscillator, which achieves a phase noise of -95 dBc/Hz@l MHz-offset at 60 GHz. The transceiver realizes IEEE802.15.3c full-rate wireless communication for all 16QAM/8PSK/QPSK/BPSK modes, and the communication distances with the full data rate using 2.16-GHz bandwidth, measured with an antenna built in the package, are 2.7-m (BPSK/QPSK) and 0.2-m (8PSK/16QAM). The measured maximum data rates are 8 Gb/s in QPSK mode and 11 Gb/s in 16QAM mode over a 5 cm wireless link within a bit error rate (BER) of <;10-3. The transceiver consumes 186 mW from a 1.2-V supply voltage while transmitting and 106 mW from 1.0-V supply voltage while receiving. Both transmitter and receiver are driven by a 20-GHz PLL, which consumes 66 mW, including output buffer, from a 1.2-V supply voltage.

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c

This paper investigates the design and implementation of millimeter-wave narrow-bandpass filters in a standard 0.18- m CMOS technology. Filters with a measured 10% 3-dB bandwidth at 60 and 77 GHz are realized in a thin-film microstrip structure by using the lowest metallization layer as a ground plane. The impact of dissipation losses of the filters is also examined. It is found that the metallization losses in the coupled-line filter as well as the ground plane are the main reasons for the insertion loss.

Design of 60- and 77-GHz Narrow-Bandpass Filters in CMOS Technology

A new equivalent-circuit model for transmission lines and inductors on silicon is proposed. The SPICE-compatible model is suitable for time-domain simulators. It is able to fit the frequency-dependent behavior of the RLGC parameters well into the millimeter-wave range. The model is extracted from electromagnetic simulations with a simple analytic procedure with no need for tuning or optimization. A method for making the model scalable with both line length and width (or inductor diameter) is proposed. Based on this new model, a scalable measurement deembedding methodology is proposed, that can greatly reduce wafer area needed for test and deembedding structures. The fully scalable model results are compared with measurements of devices fabricated in a 90 nm CMOS process.

Scalable Transmission Line and Inductor Models for CMOS Millimeter-Wave Design

A compact modeling approach for silicon-chip slow-wave transmission lines with slotted bottom metal ground planes is studied and its limitations are presented. The modeling approach facilitates the calculation of the slow-wave transmission line parameters based upon the corresponding coplanar and grounded coplanar transmission-line parameters. The described analysis method is used for a comparative study of the slow-wave structures versus their coplanar and grounded coplanar reference structures. Floating bottom shield slow-wave transmission lines are then compared with their grounded bottom shield counterparts. The theoretical results are supported by electromagnetic simulations and by measurements up to 30 and 50 GHz.

Compact Modeling and Comparative Analysis of Silicon-Chip Slow-Wave Transmission Lines With Slotted Bottom Metal Ground Planes

In general, three parameters are needed to model symmetrical adapters, but not enough equations can be found to solve them. The measurement of through adapters gives two conditions only, but neither open nor short adapter gives any useful condition. The results from lines with length L and length 2L can be used to derive the result for through adapters. This paper proposes one approach with a 2-impedance model, which has one shunt impedance and one series impedance. This model can be used with more complicated structures than the single impedance model.

https://ieeexplore.ieee.org/iel5/7648/20881/00967628.pdf

A de-embedding technique for interconnects

Three parameters are needed to model symmetrical adapters, but not enough equations can be found to solve them. The proposed two-impedance model with one shunt and one series impedance gives consistent results when applied to three different lengths of embedded microstrip transmission lines. This model can be used with more complicated structures than the single-impedance model. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 42: 50–54, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20204

G. Flynn

Papers

A de-embedding technique for interconnects

De-embedding techniques for embedded microstrips