An efficient hardware implementation of a median filter is presented. Input samples are used to construct a cumulative histogram, which is then used to find the median. The resource usage of the design is independent of window size, but rather, dependent on the number of bits in each input sample. This offers a realisable way of efficiently implementing large-windowed median filtering, as required by transforms such as the Trace Transform. The method is then extended to weighted median filtering. The designs are synthesised for a Xilinx Virtex II FPGA and the performance and area compared to another implementation for different sized windows. Intentional use of the heterogeneous resources on the FPGA in the design allows for a reduction in slice usage and high throughput.

Novel FPGA-based implementation of median and weighted median filters for image processing

Most effort in designing median filters has focused on two-dimensional filters with small window sizes, used for image processing. However, recent work on novel image processing algorithms, such as the Trace transform, has highlighted the need for architectures that can compute the median and weighted median of large one-dimensional windows, to which the optimisations in the aforementioned architectures do not apply. A set of architectures for computing both the median and weighted median of large, flexibly sized windows through parallel cumulative histogram construction is presented. The architecture uses embedded memories to control the highly parallel bank of histogram nodes, and can implicitly determine window sizes for median and weighted median calculations. The architecture is shown to perform at 72 Msamples, and has been integrated within a Trace transform architecture.

High-throughput one-dimensional median and weighted median filters on FPGA

We present a novel bit serial algorithm which is scalable and easily implemented on small FPGA chips. The basis of the algorithm is similar to that of Quicksort, and is based on a 'Bit Voter' (BV) block. The paper also extends the basic BV algorithm to include Weighted Median and Ranked Order Median filtering. The median finding unit, whose inputs are the N pixel values to sort, has an O(N) hardware complexity compared to O(N/sup 2/) complexity for an equivalent unit using Bubble sort. The novel algorithm has been implemented on an XC4010E-1 FPGA chip. For comparison purposes, we also present an FPGA implementation of an existing 'Triple Input Sorter' based algorithm (TIS) which is an optimised version of the Bubble sort algorithm for the special case of a 3/spl times/3 window size. The BV's median finding unit occupies 15 CLBs only whereas TIS occupies 60 CLBs. For 512/spl times/512 input images of 8-bit/pixel, comparative timings show that BV can operate at 25 frames per second (fps), while TIS can achieve 39 fps. Thus, both algorithms can achieve real time performance, and BV is the more compact.

Design and implementation of a novel algorithm for general purpose median filtering on FPGAs

In digital image processing systems, the acquisition stage may capture impulsive noise along with the image. This physical phenomenon is commonly referred to as “salt-and-pepper” noise. The median filter is a nonlinear image processing operation used to remove this impulsive noise from images. This digital filter can be implemented in hardware to speed up the algorithm. However, an SRAM-based field-programmable gate array implementation of this filter is then susceptible to configuration memory bit flips induced by single event upsets, so a protection technique is needed for critical applications in which the proper filter operation must be ensured. In this paper, a fault-tolerant implementation of the median filter is presented and studied in-depth. Our protection technique checks if the median output is within a dynamic range created with the remaining nonmedian outputs. An output error signal is activated if a corrupted image pixel is detected, then a partial or complete reconfiguration can be performed to remove the configuration memory error. Experimental results show that our technique detects enough corrupted pixels in an image to prevent 91% of the corrupted images from being erroneously sent to the next image processing operation. This high error detection rate is achieved introducing only a 35% of additional resource overhead.

Error Detection Technique for a Median Filter

This paper introduces a novel neural architecture which is capable of similar performance to any of the "classic" neural paradigms while having a very simple and efficient mixed-signal implementation which makes it a valuable candidate for intelligent signal processing in portable multimedia applications. The architecture and its realization circuit are described and the functional capabilities of the novel neural architecture called a simplicial neural cell are demonstrated for both regression and classification problems including nonlinear image filtering.

The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications

The median filter is an effective device for the removal of impulse-based noise on video signals. This is due to the partial averaging effect of the median filter and its biasing of the input stream, rather than straight mathematical averaging. In this paper, we describe three realizations of median filter, built into as few as one field programmable logic device, which is capable of processing an incoming video data stream at a maximum (programmable logic device partially dependent) of around 30 MS/s. In total, four designs are considered, with a primary design, two variations on the primary design and an asynchronous version based on the primary design. Simulation of the primary design (both synchronous and asynchronous) has demonstrated its potential for reducing the area requirements of a median filter whilst not sacrificing either speed or accuracy.

G.L. Bates

Papers

FPGA implementation of a median filter